Foenix F256 / Wildbits/K2 Wiki - User contributions [en]

65816 Overview

2024-06-02T21:10:28Z

97.113.38.170: more URL formatting nonsense.

= Introduction =
The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended data transfers. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

= Upgrading =
The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:
* You must use a 65C816SP part; slower models will not work.
* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

= Programming =

* The standard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.
<nowiki>
; If this is a 65816, switch pin 3 from an input
; (for PHI0-out) to a 1 output (for ABORTB-in).
.cpu "65816"
clc
xce
bcc +
sec
xce
stz $1
lda #$03
sta $d6b0
+ .cpu "w65c02"
</nowiki>

* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: https://wiki.c256foenix.com/index.php?title=C256

= Kernel Support =
* The [[MicroKernel]] does not support the 816 running in native mode. You can still use the enhanced instructions in emulation mode, and you can temporarily switch to native mode while interrupts are disabled, but note that such software will not run correctly on standard 65c02 machines.
* The [[OpenFNXKernal]] endeavors to function correctly in both modes.

= Historical Notes =

Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

The "65" in the part's designation comes from its 65C02 compatibility mode, and the "816" signifies that the MPU has selectable 8-bit and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new control signals for improved system hardware management.

Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.

At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.

User programs can then switch the W65C816 to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 - Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.

The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).

(#) ''This point (noted from the main site F256K ordering page), needs more explanation by someone more knowledgable on F256 operation with a W65C816 processor installed.''

65816 Overview

2024-06-02T21:09:32Z

97.113.38.170: The C256 wiki link needs a different format.

= Introduction =
The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended data transfers. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

= Upgrading =
The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:
* You must use a 65C816SP part; slower models will not work.
* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

= Programming =

* The standard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.
<nowiki>
; If this is a 65816, switch pin 3 from an input
; (for PHI0-out) to a 1 output (for ABORTB-in).
.cpu "65816"
clc
xce
bcc +
sec
xce
stz $1
lda #$03
sta $d6b0
+ .cpu "w65c02"
</nowiki>

* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: [C256|https://wiki.c256foenix.com/index.php?title=C256]

= Kernel Support =
* The [[MicroKernel]] does not support the 816 running in native mode. You can still use the enhanced instructions in emulation mode, and you can temporarily switch to native mode while interrupts are disabled, but note that such software will not run correctly on standard 65c02 machines.
* The [[OpenFNXKernal]] endeavors to function correctly in both modes.

= Historical Notes =

Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

The "65" in the part's designation comes from its 65C02 compatibility mode, and the "816" signifies that the MPU has selectable 8-bit and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new control signals for improved system hardware management.

Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.

At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.

User programs can then switch the W65C816 to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 - Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.

The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).

(#) ''This point (noted from the main site F256K ordering page), needs more explanation by someone more knowledgable on F256 operation with a W65C816 processor installed.''

65816 Overview

2024-06-02T21:08:34Z

97.113.38.170: Added link to the C256 wiki for users experimenting with the 816e FPGA load for the Jr.

= Introduction =
The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended data transfers. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

= Upgrading =
The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:
* You must use a 65C816SP part; slower models will not work.
* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

= Programming =

* The standard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.
<nowiki>
; If this is a 65816, switch pin 3 from an input
; (for PHI0-out) to a 1 output (for ABORTB-in).
.cpu "65816"
clc
xce
bcc +
sec
xce
stz $1
lda #$03
sta $d6b0
+ .cpu "w65c02"
</nowiki>

* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: [[C256|https://wiki.c256foenix.com/index.php?title=C256]]

= Kernel Support =
* The [[MicroKernel]] does not support the 816 running in native mode. You can still use the enhanced instructions in emulation mode, and you can temporarily switch to native mode while interrupts are disabled, but note that such software will not run correctly on standard 65c02 machines.
* The [[OpenFNXKernal]] endeavors to function correctly in both modes.

= Historical Notes =

Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

The "65" in the part's designation comes from its 65C02 compatibility mode, and the "816" signifies that the MPU has selectable 8-bit and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new control signals for improved system hardware management.

Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.

At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.

User programs can then switch the W65C816 to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 - Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.

The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).

(#) ''This point (noted from the main site F256K ordering page), needs more explanation by someone more knowledgable on F256 operation with a W65C816 processor installed.''

Hardware

2024-05-28T19:22:07Z

97.113.38.170: Fixed typo

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
! scope="row"; style="text-align:left;" |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB SRAM 
128 MB DRAM 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky
|
TinyVicky
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (SN76489) 
2 x SID socket 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
SAM2695 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x virtual Serial Port (available over USB) 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816_Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Ouput Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilising the Expension Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Hardware

2024-05-27T19:38:47Z

97.113.38.170: Added initial F256k2 specs to the hardware comparison table. - gadget.

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
! scope="row"; style="text-align:left;" |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB SRAM 
128 MB SRAM 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky
|
TinyVicky
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (SN76489) 
2 x SID socket 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
SAM2695 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x virtual Serial Port (available over USB) 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816_Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Ouput Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilising the Expension Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Software for 6502

2024-01-17T06:57:10Z

97.113.38.170: /* Utilities */

Note that when an hex address is given, it's meant to instruct as to which address to bload or to send (ie foenixmgr python script) the program (ie a .bin file) to before running it.

Many download links are posts in the main [https://discord.gg/9vjUEGgcUS Foenix Retro Systems discord server] which will require you to join in order to get to them.

A [[Getting Started#Demos Archive|Demo Archive]] was put together in September 2023 to get ready to show to youtubers, some of these are linked once more, in this page.

There's also the Foenix Marketplace website maintained by EMWhite with its own collection of articles and software http://apps.emwhite.org/foenixmarketplace/.

== Applications ==
{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|F256-GraphicToolkit
|Sprite editor, Tilemap editor, Font editor + misc tools
|econtrerasd
|basic
|https://github.com/econtrerasd/F256-GraphicToolkit
|}

== Demos ==
{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|balls
|Draw a good quantity of multiplexed sprites, fast. Balls bouncing around
|celton
|pgz
|https://github.com/FoenixRetro/demos/blob/main/MultiplexedSprites.md
|-
|F256 Mandelbrot
|Draws Mandelbrot set fast (5 mins) using coprocessor math
|mgr42
|uses basic loader
|https://github.com/rmsk2/F256_Mandelbrot
|-
|F256ShowCase
|Shows sliding tiling graphics, moves with joystick
|eriktier
|$0000
|https://github.com/pig-games/F256Showcase
|-
|fnxmas23
|PSG mod music, scrolling text, sound effects, must see demo!
|dwsJason and digarok
|pgz
|https://discordapp.com/channels/691915291721990194/934618943400837130/1188633998663098398 if you have Dec23 FPGA load or newer
https://discordapp.com/channels/691915291721990194/934618943400837130/1188633118194794527 if you have an older FPGA load
|-
|foenixmas23
|Xmas 2023 demo with SID music from the classic 1983 C64 xmas demo
|EMWhite
|uses basic loader
|http://apps.emwhite.org/shared-files/815/?foenixmas23.zip
|-
|livingworlds
|Living Worlds, a port of a color cycling by Mark Ferrari, ported here on the F256 by haydenkale
|haydenkale
|$0000
|https://github.com/clandrew/livingworlds/tree/e4532e0d530b76ccb90368fdf5ad10bfa2deeb12
|-
|mandel
|Will draw a mandelbrot set in 3 hours, more useful as a stability test than a useful fractal program
|Mu0n
|basic
|https://github.com/Mu0n/F256KbasicBASICdoodles?tab=readme-ov-file#fractal
|-
|wormhole
|Shows a fast wireframe animation of a wormhole
|haydenkale
|pgz or bin at $0000
|https://github.com/clandrew/wormhole?tab=readme-ov-file
|}

== Games ==

{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|Bombsweeper
|Bomb sweeper port
|beethead
|pgz
|https://discord.com/channels/691915291721990194/855689509520932885/1196352934083035156
|-
|Cosmic
|Shoot 'em up
|beethead
|pgz
|https://discordapp.com/channels/691915291721990194/1054250238308790342/1175982979537969214
|-
|F256 two to the power of eleven
|Port of the puzzle game of 2048
|mgr42
|$2500
|https://github.com/rmsk2/F256_2048<nowiki/>https://discordapp.com/channels/691915291721990194/1054250238308790342/1195738663565402112
|-
|Jr Wördl
|port of Wordle
|AgeAgeEye
|basic
|https://github.com/ageageeye/Superbasic-F256Jr-examples
|-
|Ski-Jr
|Ski game downhill
|digarok
|basic
|https://github.com/digarok/superbasic-traveler/blob/main/ski-jr.bas
|}

== Music ==

{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|EdInHisLib
|SID+OPL3 simultaneously
|beethead, ported from xantax
|pgz
|F256 port: https://discordapp.com/channels/691915291721990194/1054249926521016392/1184413356598231120
original: <nowiki>https://csdb.dk/release/?id=170898</nowiki>. Not 100% accurate but close.
|-
|jrtracker
|Tracker based in basic and uses the PSG
|contrerasd
|basic
|https://ptb.discord.com/channels/691915291721990194/1008139105386889346/1188292876984143983
|-
|modo
|MOD player using the PSG
|dwsJason and digarok
|pgz
|https://discordapp.com/channels/691915291721990194/855689509520932885/1190723114661859429
|-
|piano
|Plays some PSG notes with the keyboard
|Mu0n
|basic
|https://github.com/Mu0n/F256KbasicBASICdoodles?tab=readme-ov-file#pulse-sound-generator-piano
|}

== Utilities ==

{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|wget
|fetches a file from a http address if you have a network connection active
|gadget
|pgz/flash
|https://github.com/ghackwrench/F256_wget
|}

== Sample Code ==

{| class="wikitable"
|+
!Program
!Description
!Author
!Notes on running
!Link
|-
|cc65 example
|c example code
|gadget
|read github
|https://github.com/ghackwrench/F256_Jr_Kernel_DOS
|-
|digarok basic stuff
|Lots of basic examples
|digarok
|read github
|https://github.com/digarok/superbasic-traveler/tree/main
|-
|Mu0n's F256K basic doodles
|Some basic examples
|Mu0n
|read github
|https://github.com/Mu0n/F256KbasicBASICdoodles
|-
|tcp example
|connects to a server and gets typed in text echoed back to you
|gadget
|$2000
|https://github.com/ghackwrench/F256_example_tcp
|}

Getting Started

2024-01-14T20:50:53Z

97.113.38.170: /* SuperBASIC */

== Getting Powered Up ==

=== Powering your F256K ===

The F256K is powered via a standard 2.5mm DC Connector, which takes a centre-positive 12V 2A capable Power Supply.

This type of power supply is quite common. [https://www.amazon.com/Adapter-100-240V-Transformer-Charger-Security/dp/B091XSVV1Y Example 12V 2A capable power supply] (#)

(#) ''This specific power supply has not been verified (by the author) for use with the F256K. Please update this page with verified options!''

=== Powering your F256Jr ===

The F256Jr is supplied as a Mini-ITX form factor mainboard, with a standard 24 pin ATX power supply connector for power connectivity.

Since the F256Jr needs relatively little power, compared to a mini-ATX PC, a popular DC 12V 24pin Pico ATX PSU works well and is a compact solution.

* [https://www.amazon.com/dp/B08F57GKCL Pico PSU] - You power the Pico PSU via a 12V DC center-positive Power Supply source.
* [https://www.amazon.com/dp/B07MXXXBV8 12V DC center-positive A/C Adapter] - Commonly used to power the Pico PSU.

== Getting programs onto the F256 ==

=== SD Card ===

Both the F256K and F256JR have an SD card slot. The device software to read the SD card is a bit touchy (it's inherited from the Commander X16 project) and doesn't work with all SD cards

* Cards should support the V2 protocol (HC or XC); older cards that only support the V1 protocol (typically 2GB or less) won't work. By contrast, the kernels for the C256 machines generally only work with V1 cards. Note that, in both cases, this is a software limitation -- all of the Foenix machines are electrically capable of using both kinds of cards.
* Cards *MUST* be formatted FAT32 -- **NOT: FAT, FAT12, FAT16, or exFAT**. Note that while MacOS will read a FAT32 formatted card, the included disk utility won't format FAT32. Windows 10/11 works fine, but make sure to force FAT32 (or use the command line: <code>format /FS:FAT32 H:</code>)
* Some folks have had luck formatting cards with the [https://www.sdcard.org/downloads/formatter/sd-memory-card-formatter-for-windows-download/ Official SD Association formatter for Windows].

=== Demos Archive ===

* [https://github.com/FoenixRetro/Documentation/blob/main/f256/archive Download the most recent demos archive] and expand it to the root of the flash card.

=== Debug USB port ===

* This is what most developers use as it's the most convenient. Connect the debug USB port to your PC or Mac

* You can use:
** [https://github.com/pweingar/FoenixMgr FoenixMgr] - works on Windows, Mac, Linux
*** A Python script to manage the Foenix series of retro style computers through their USB debug ports. This tool allows uploading files of various formats to system RAM, and displaying memory through various means.

** [https://github.com/Trinity-11/FoenixIDE FoenixIDE] (Windows only)
*** Development and Debugging Suite for the C256 Foenix Family of Computers.

=== wget ===
If you have the [[wifi]] configured, you can use [https://github.com/ghackwrench/F256_wget wget] to pull programs and data right off the web!

== SuperBASIC ==

The machine boots to SuperBASIC. SuperBASIC is inspired by BBC BASIC but offers quite a bit more.

* Read the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual].

* Watch EMWhite's excellent intro series on Youtube:
** Full Playlist here: [https://www.youtube.com/playlist?list=PLeHjTvk7NPiSqGz4REMH-S4hjYpLS2YNR EMWhite's Intro Series - Full Playlist].
** Part 1 can be viewed here:
<youtube>G_S2c_MsqYA</youtube>

To get started, you can type in a sample program at the command prompt:

<pre>
10 for i=1 to 5
20 print "Hello world"
30 next
run
</pre>

SuperBASIC is similar to CBM (Microsoft) BASIC but has some differences. For example, note in the sample above it's just <code>next</code> not <code>next i</code>.

The first 15 or so pages of the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual] are quite instructive.

SuperBASIC is actually much more powerful and supports structured programming (procedures, blocks etc.)

<code>dir</code> - Run this to display directory of SD card

Loading & running programs off of the SD card is similarly easy:

<pre>
load "JrWordl.bas"
run
</pre>

Similar to the C64, you can save time in loading programs from the <code>dir</code> listing by using your cursor keys to go up to the entry, typing <code>load "</code> (insert mode is active by default) etc. You can use <code>CTRL+E</code> to jump to the end of the line and use <code>CTRL+K</code> to delete any text from the cursor to the end of the line. Correctly place the closing <code>"</code> and hit <code>ENTER</code>.

<code>CTRL+C</code> acts as a "break" command and stops any running SuperBASIC program or <code>LIST</code> command.

Read built-in help/reference:

<code>/help</code> : But '''NOTE''', this erases BASIC memory! Use Backspace key to go back in menus and to exit.

Explore the included demo SuperBASIC programs:

{| class="wikitable"
! Program !! Notes !! Source
|-
| <code>JrWordl.bas</code> || Wordle game, guess 5 letter word ||
|-
| <code>mandel.bas</code> || Draws Mandlebrot set in graphics mode, takes between 2 and 3 hours || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>rpg-demo.bas</code> || UI sample that shows Zelda like RPG game. Control the character with an Atari-joystick connected to JoyPort1 || @econtrerasd
|-
| <code>Problematic_Code.bas</code> || Displays scrolling starfield ||
|-
| <code>noelrl.bas</code> || Simple integer BASIC bench mark from Noel's retro lab. Completes < 3.5 seconds, compares very favourably to other retro systems! || [https://www.youtube.com/watch?v=H05hM_Guoqk Youtube]
|-
| <code>dance.bas</code> || Animates sprite of dancer || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>luna.bas</code> || Displays simple scene ||
|-
| <code>blink.bas</code> || Blinks drive access light || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>piano.bas</code> || Play some notes with the PSG || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|}

== Native Code ==

* Binary programs for the F256 line are typically distributed as <code>pgx</code> or <code>pgz</code> files (see [[File Formats]], they are like the <code>prg</code> format in the C64 ecosystem).

* SuperBASIC: Slash (<code>/</code>) command will execute the named flash resident program, such as <code>/dos</code> or <code>/help</code> (SuperBASIC reference).

* PGZ/X files can be run from SuperBASIC with <code>/- program.pgz</code>, and from DOS with <code>- program.pgz</code>

* The <code>-</code> is also referred to as <code>pexec</code>, and is a chainloader that understands <code>pgx</code> and <code>pgz</code> formats, so <code>/- program.pgz</code> first hands over control to <code>pexec</code> which then loads the program and hands over control.

* You will typically need to reset the machine to get back to SuperBASIC.

* Switch to DOS with <code>/dos</code> and back into BASIC once there with <code>basic</code>. <code>help</code> display a list of available DOS commands.

Try the included native demo programs:

{| class="wikitable"
! Program !! Notes !! Source |
|-
| <code>wrtn0825-vcf.pgz</code> || Which Rules the Night (game) || @beethead
|-
| <code>matchit0825-vcf.pgz</code> || Match It (game) || @beethead
|-
| <code>balls.pgz</code> || Demonstrates 280 multiplexed sprites || [https://github.com/FoenixRetro/demos/blob/main/README.md GitHub]
|}

== More Resources ==

=== This Wiki ===

Explore all of the content of this Wiki, to expand your F256 series knowledge!

=== Discord ===

The [https://discord.com/invite/aAEQXZHXgM Foenix Retro Systems Discord] is the primary place to get questions answered.

Also, if you resolve your question, and you didn't find the answer here on the Wiki, '''''please consider contributing to the Wiki''''', for the benefit of others with the same question!

=== Foenix Retro Systems Newletter ===

Read back issues [http://apps.emwhite.org/foenixmarketplace/ here] (also a great source for sample programs).

Issues starting at #4 cover the F256 line. Issues 1-3 cover the previous version of the hardware (C256), although there are still many salient points.

SuperBASIC

2024-01-14T20:50:27Z

97.113.38.170:

SuperBASIC is inspired by BBC BASIC but offers quite a bit more.
* [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual].
* [[SuperBASIC Memory Map]]
* Watch EMWhite's excellent intro series on YouTube: [https://www.youtube.com/playlist?list=PLeHjTvk7NPiSqGz4REMH-S4hjYpLS2YNR Full Playlist].

SuperBASIC Memory Map

2024-01-14T20:47:46Z

97.113.38.170: Memory map, moved from Getting Started.

=== Memory Map under BASIC ===
{| class="wikitable sortable"
|+ Caption text
|-
! Initial Address !! End Address !! Description !! Bytes
|-
| $0000|| -|| MMU Control Register || 1
|-
| $0001|| -|| I/O Control Register || 1
|-
| $0002|| $0007|| Free Zero Page Addresses || 6
|-
| $0008|| $000F|| MMU Control Addresses || 8
|-
| $0010|| $002F|| Free Zero Page Addresses || 32
|-
| $0030|| $003F|| Used Zero Page Addresses for (xx),Y Addressing || 16
|-
| $0040|| $0041 || Current Address on screen of start of line || 2
|-
| $0042|| $004F|| Avaliable Zero Page Addresses || 14
|-
| $0050|| $00AF|| Number / Floating Point Stack for 16 numbers || 96
|-
| $00B0||$00EF|| Available Zero Page || 64
|-
| $00F0|| $00FF|| Kernel Arguments in Zero Page || 16
|-
| $0100|| $01FF|| Hardware Stack of 6502 || 256
|-
| $0200|| $0228|| Basic mini-Kernel memory || 40
|-
| $0229|| $03FF|| Available Low Memory | Also used by Sound Command in BASIC || 470
|-
| $0400|| $041F|| Control Storage first 8 bytes control syntax highlighting || 32
|-
| $0420|| $0814|| Memory Storage || 1012
|-
| $0814|| $0FFF|| Available Low Memory || 2027
|-
| $1000|| $1FFF|| SuperBASIC Identifier Tables, allocated memory, string vars, stack || 4kb
|-
| $2000|| $77FF|| SuperBASIC Program Tokenized Code (grows Upward) || 22kb
|-
| $7800|| $7FFF|| Top 2k of SuperBASIC Program tokenize code or used for ML routines in low memory || 2kb
|-
| $8000|| $BFFF|| SUPERBASIC CODE || 16kb
|-
| $C000|| $DFFF|| I/O Memory Pages / Underlying Kernel Code (Selectable with I/O control Register)|| 8kb
|-
| $E000|| $FFEF|| KERNEL CODE || 8176
|-
| $FFF0|| $FFFF|| Reset Vectors and NMI / IRQ / BRK Vectors || 16
|-
| $01:0000|| $02:2BFF|| Default Memory used by BASIC bitmap graphics || 75kb
|-
| $02:2C00|| $02:7FFF|| Available High Memory || 21kb
|-
| $02:8000|| $02:F000|| Available High Memory | Used for BASIC Cross Development w/PC or MAC|| 32k
|-
| $03:0000|| $03:7FFF|| Used for Sprite Data in BASIC || 32kb
|-
| $03:8000|| $03:FFFF|| Available High Memory | Unless not running from Flash, Used for ROM Images|| 32k
|-
| $04:0000|| $07:DFFF|| Available High Memory || 248kb
|-
| $07:E000|| $07:FFFF|| Available High Memory | Being considered to be Reserved for Environmental Variables || 8Kb
|-
| $10:0000|| $13:FFFF|| Cartridge Expanded Memory (addresable only by CPU) || 256kb
|-
| $14:0000|| $1F:FFFF|| Future Expansions? || 768kb
|}

SuperBASIC

2024-01-14T20:46:56Z

97.113.38.170: Initial stand-alone SB page.

SuperBASIC is inspired by BBC BASIC but offers quite a bit more.
* [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual].
* [[SuperBASIC Memory Map]]
* Watch EMWhite's excellent intro series on Youtube:
** Full Playlist here: [https://www.youtube.com/playlist?list=PLeHjTvk7NPiSqGz4REMH-S4hjYpLS2YNR EMWhite's Intro Series - Full Playlist].