Foenix F256 / Wildbits/K2 Wiki - User contributions [en]

Main Page

2025-10-09T23:32:46Z

Foenix: Protected "Main Page" ([Edit=Allow only administrators] (indefinite) [Move=Allow only administrators] (indefinite))

<div id="mainpage"></div> __NOTOC__ __NOEDITSECTION__


<div style="margin: 0 0 15px 0; padding: 1px; border: 1px solid #CCCCCC;">
{| style="width: 100%; margin: 0; padding: 0; border: 0; background-color: #FCFCFC; color: #000000; border-collapse: collapse;"
| align="center" style="vertical-align: top;"|
<div style="font-size: 150%;">Welcome to the Foenix Retro Systems' F256x series Wiki</div>
<div style="font-size: 100%; margin-top: 0.7em; line-height: 130%;">Dedicated to the WDC65C02/WDC65C816 or FNX6809 based F256x series.</div>
|}
</div>


{| style="width: 100%; margin: 0; padding: 0; border: 0; border-collapse: collapse;"
| style="padding: 0; width: 25%; vertical-align: top;" |


{{NocatBox|subject=Getting Started|page=Main2/Getting_Started}}
{{NocatBox|subject=How To|page=Main2/How_To}}
{{NocatBox|subject=Technical Overview|page=Main2/Technical_Overview}}
{{NocatBox|subject=System Maintenance|page=Main2/System_Maintenance}}

| style="padding: 0 0 0 10px; width: 25%; vertical-align: top;" |


{{NocatBox|subject=Software Development|page=Main2/Software_Development}}
{{NocatBox|subject=Utility Software|page=Main2/UtilitiesPage}}
{{NocatBox|subject=W65C816 Processor|page=Main2/65816_Processor}}
{{NocatBox|subject=FNX6809 Processor|page=Main2/FNX6809_Processor}}
{{NocatBox|subject=Game Development|page=Main2/Game_Development}}
|}

Main Page

2025-10-09T23:30:27Z

Foenix: Removed protection from "Main Page"

Use the Core2x

2025-08-07T20:10:28Z

Foenix: Put in place link to a Linode Bucket to download the PDF File

New Features Documentation for the Core2x for K2 and Jr2

[https://256-foenix.us-east-1.linodeobjects.com/F256K2x_Cores%2FCore2x_ShortFormSpec_Aug7th.pdf Core2x_ShortForm_Documentation]

Use the Core2x

2025-07-12T08:37:25Z

Foenix: Introduction to the new page describing the feature of the Core2x for K2 and Jr2

New Features Documentation for the Core2x for K2 and Jr2

CPU @ 12Mhz

SRAM Bus @ 16bits Wide

Bit Definition $0000

Bit Definition $0001

Memory Text Mode

Line Drawing

DMA Modes

Floating-Point Module

Sprites Expansion

Template:Main2/How To

2025-07-11T07:22:54Z

Foenix: Add a new page to describe the functionality of the Core2x

'''How To Program these Devices'''
* [[Use the CODEC]]
* [[Use the K2 LCD]]
* [[Use the LEDs]]
* [[Use the PS/2 Mouse]]
* [[Use the PSG]]
* [[Use the Sam2695 Dream MIDI chip]]
* [[Use the SNES/NES controllers]]
* [[Use the VS1053b chip]]
* [[Use the Core2x]]

Use Core2x

2025-07-11T07:17:36Z

Foenix: Created page with "== How to use the New Core2x == The Codec chip is a way to mix and match audio signals together for their single audio output (headphones, RCA jacks). Its datasheet can be found in the goodies github repo: https://github.com/Mu0n/F256MiscGoodies/blob/main/datasheets/WM8776_v4.1-532420.pdf === Codec Registers === {| class="wikitable" ! Address !! R/W !! B7 !! B6 !! B5 !! B4 !! B3 !! B2 !! B1 !! B0 !! Purpose |- | 0xD620 || W|| D7|| D6|| D5|| D4|| D3|| D2|| D1|| D0|| C..."

== How to use the New Core2x ==

The Codec chip is a way to mix and match audio signals together for their single audio output (headphones, RCA jacks).

Its datasheet can be found in the goodies github repo: https://github.com/Mu0n/F256MiscGoodies/blob/main/datasheets/WM8776_v4.1-532420.pdf

=== Codec Registers ===

{| class="wikitable"
! Address !! R/W !! B7 !! B6 !! B5 !! B4 !! B3 !! B2 !! B1 !! B0 !! Purpose
|-
| 0xD620 || W|| D7|| D6|| D5|| D4|| D3|| D2|| D1|| D0|| Command Low
|-
| 0xD621 || W || R6|| R5|| R4|| R3|| R2|| R1|| R0|| D8|| Command High
|-
| 0xD622 || R|| X|| X|| X|| X|| X|| X|| X|| Busy|| Status
|-
| 0xD622 || W|| X|| X|| X|| X|| X|| X|| X|| Start|| Control
|}

=== How to enable (unmute) every sound device ===

* Loop-read 0xD622 and wait until bit0 is set to 1
* Send 0x1F to Command Low at 0xD620
* Send 0x2A to Command High at 0xD621
* Loop-read 0xD622 and wait until bit0 is set to 1

=== Audio input devices on the various machines ===

{| class="wikitable"
! CODEC inputs !! F256Jr !! F256K !! F256K2 !! F256Jr2
|-
| AIN1|| SID|| SID|| SAM2695 MIDI|| SAM2695 MIDI
|-
| AIN2|| Line in onboard header || OPL3|| MIDI wavetable||
|-
| AIN3|| || || PWM|| PWM
|-
| AIN4|| || || VS1053b|| VS1053b
|-
| AIN5|| || Line in onboard header|| Line in onboard header|| Line in onboard header
|}

MID codes for machine identification

2025-06-25T09:23:05Z

Foenix: /* MID codes for machine identification */

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 is unused for this process.

Bit 7 has been dedicated for the 2x CPU speed cores. When set, it indicates the CPU runs at 12 MHz.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit7
!Bit6
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
| -
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
| -
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
| -
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|0
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|0
|'''(0x82) 0x02'''
|'''65816'''
|'''F256 Jr. MMU & Ext (816 Only) with 2x speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0x22) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0xA2) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with MMU & Ext (816 Only) 2x Speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|0
| -
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
| -
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
| -
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
| -
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
| -
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
| -
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
| -
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
| -
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
| -
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
| -
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
| -
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
| -
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
| -
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
| -
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|'''1'''
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11 (0x91)'''
|'''65816'''
|'''F256K2 with MMU & Ext x2 CPU Core'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|'''1'''
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12 (0x92)'''
|'''6502/65816/6809'''
|'''F256K with MMU & Ext (816 Only) x2 CPU'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
| -
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
| -
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
| -
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
| -
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-06-25T08:37:02Z

Foenix: /* MID codes for machine identification */

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 is unused for this process.

Bit 7 has been dedicated for the 2x CPU speed cores. When set, it indicates the CPU runs at 12 MHz.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit7
!Bit6
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
| -
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
| -
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
| -
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|0
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|0
|'''(0x82) 0x02'''
|'''65816'''
|'''F256 Jr. MMU & Ext (816 Only) with 2x speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0x22) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0xA2) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with MMU & Ext (816 Only) 2x Speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|0
| -
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
| -
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
| -
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
| -
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
| -
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
| -
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
| -
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
| -
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
| -
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
| -
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
| -
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
| -
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
| -
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
| -
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
| -
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
| -
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
| -
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
| -
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-06-25T08:35:56Z

Foenix: /* MID codes for machine identification */

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 is unused for this process.

Bit 7 has been dedicated for the 2x CPU speed cores. When set, it indicates the CPU runs at 12 MHz.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit7
!Bit6
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
| -
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
| -
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
| -
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|0
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|0
|'''(0x82) 0x02'''
|'''65816'''
|'''F256 Jr. Classic MMU & Ext with 2x speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0x22) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0xA2) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816) 2x Speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|0
| -
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
| -
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
| -
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
| -
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
| -
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
| -
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
| -
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
| -
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
| -
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
| -
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
| -
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
| -
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
| -
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
| -
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
| -
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
| -
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
| -
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
| -
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-06-25T08:32:33Z

Foenix: /* MID codes for machine identification */

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 is unused for this process.

Bit 7 has been dedicated for the 2x CPU speed cores. When set, it indicates the CPU runs at 12 MHz.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit7
!Bit6
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
| -
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
| -
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
| -
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|0
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|0
|'''(0x82) 0x02'''
|'''65816'''
|'''F256 Jr. Classic MMU & Ext with 2x speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''(0x22) 0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|0
| -
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
| -
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
| -
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
| -
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
| -
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
| -
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
| -
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
| -
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
| -
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
| -
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
| -
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
| -
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
| -
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
| -
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
| -
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
| -
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
| -
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
| -
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-06-22T07:59:27Z

Foenix: /* MID codes for machine identification */ Update the Jr Entry for the new 12Mhz 816 Core

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 is unused for this process.

Bit 7 has been dedicated for the 2x CPU speed cores. When set, it indicates the CPU runs at 12 MHz.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit7
!Bit6
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
| -
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
| -
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
| -
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|0
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
| -
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|0
|'''0x02'''
|'''65816'''
|'''F256 Jr. Classic MMU & Ext with 2x speed'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|0
| -
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|0
| -
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
| -
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
| -
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
| -
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
| -
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
| -
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
| -
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
| -
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
| -
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
| -
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
| -
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
| -
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
| -
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
| -
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
| -
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|0
| -
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
| -
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
| -
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
| -
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-03-07T00:18:57Z

Foenix:

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 to 7 are unused for this process.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|'''''F256K2 with 68K Core (FA2560K2) $$$'''''
|-
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-03-07T00:18:32Z

Foenix:

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 to 7 are unused for this process.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|'''''0'''''
|'''''1'''''
|'''''1'''''
|'''''0'''''
|'''''0'''''
|'''''0'''''
|'''''0x18'''''
|'''''68000'''''
|''F256K2 with 68K Core (FA2560K2) $$$''
|-
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

MID codes for machine identification

2025-03-07T00:17:21Z

Foenix: Introduction of a new MID (an upcoming core)

== MID codes for machine identification ==
These are useful in order to support the different machines within the F256 class of machines, as they don't have the exact same devices, sound options and whatnot. For a detailed list of what is supposed to be available, read on this page [[Hardware| on hardware details]].
Additionally, the specific FPGA core that is currently running will affect the following ID that is found in this table. For completeness, other computers from the Foenix Retro Systems are included, but they are not otherwise covered in this wiki you're currently reading. The current wiki tries to cover the F256Jr., F256K, F256 Jr.Jr. and F256K2. For all other computers mentioned in this table, you can refer to the older wiki found at [[https://wiki.c256foenix.com/index.php?title=Main_Page | wiki.c256foenix.com]].

To get one of the following Machine ID, check the read-only register address of 0xD6A7 and check bits from 0 to 4. Initially, a 0x1F mask was applied to the value read from 0xD6A7.

However, bit 5 was recently added to account for some cores of the Jr.2 so that they are different from the equivalent of the original Jr. Bits 6 to 7 are unused for this process.

{| class="wikitable" style="text-align:left;" ;
|- style="vertical-align:top;"
!Bit5
!Bit4
!Bit3
!Bit2
!Bit1
!Bit0
!Hex using 0x1F mask
!CPU
!Machine
|-
|0
|0
|0
|0
|0
|0
|0x00
|65816
|C256 FMX
|-
|0
|0
|0
|0
|0
|1
|0x01
|65816
|C256 U
|-
|0
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x02'''
|'''6502/65816/6809'''
|'''F256 Jr. with classic mmu'''
|-
|'''0'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr. extended memory map'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x02'''
|'''65816'''
|'''F256 Jr.Jr. with classic mmu (65816)'''
|-
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x03'''
|'''65816'''
|'''F256 Jr.Jr. with extended memory map (65816)'''
|-
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0x1A'''
|'''6809'''
|'''F256 Jr.Jr. with 6809 core'''
|-
|0
|0
|0
|1
|0
|0
|0x04
|65816
|Gen X
|-
|0
|0
|0
|1
|0
|1
|0x05
|65816
|C256 U+ (4M SRAM)
|-
|0
|0
|0
|1
|1
|0
|0x06
|
|Reserved
|-
|0
|0
|0
|1
|1
|1
|0x07
|
|Reserved
|-
|0
|0
|1
|0
|0
|0
|0x08
|68xx0xx
|A2560 X (GenX 32Bits Side)
|-
|0
|0
|1
|0
|0
|1
|0x09
|68EC000
|A2560 U+
|-
|0
|0
|1
|0
|1
|0
|0x0A
|68LC060
|A2560 M (launch in 2025)
|-
|0
|0
|1
|0
|1
|1
|0x0B
|68040RC25V
|A2560 K (classic)
|-
|0
|0
|1
|1
|0
|0
|0x0C
|68040FE33V
|A2560 K40
|-
|0
|0
|1
|1
|0
|1
|0x0D
|68LC060
|A2560 K60
|-
|0
|0
|1
|1
|1
|0
|0x0E
|
|Undefined
|-
|0
|0
|1
|1
|1
|1
|0x0F
|
|Undefined
|-
|0
|1
|0
|0
|0
|0
|0x10
|65816
|F256P (future portable?)
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0'''
|'''1'''
|'''0x11'''
|'''65816'''
|'''F256K2 with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''0'''
|'''0x12'''
|'''6502/65816/6809'''
|'''F256K with classic mmu map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''1'''
|'''1'''
|'''0x13'''
|'''6502/65816'''
|'''F256K with extended map'''
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''0'''
|'''0'''
|'''0x14'''
|'''65816'''
|'''F256K2 with extended map'''
|-
|0
|1
|0
|1
|0
|1
|0x15
|
|Reserved
|-
|'''0'''
|'''1'''
|'''0'''
|'''1'''
|'''1'''
|'''0'''
|'''0x16'''
|'''6809'''
|'''F256K2 with 6809 core'''
|-
|0
|1
|0
|1
|1
|1
|0x17
|
|Reserved
|-
|0
|1
|1
|0
|0
|0
|0x18
|68K
|F256K2 with 68K Core (FA2560K2) $$$
|-
|0
|1
|1
|0
|0
|1
|0x19
|
|Reserved
|}

=== Additional registers for machine information ===

Note that these are all read-only registers.

{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
!Address
!Name
!Description
|-
|0xD6A8
|PCBID0
|ASCII character 0: "B"
|-
|0xD6A9
|PCBID1
|ASCII character 0: "0"
|-
|0xD6AA
|CHSV0
|TinyVicky subversion in BCD (low)
|-
|0xD6AB
|CHSV1
|TinyVicky subversion in BCD (high)
|-
|0xD6AC
|CHV0
|TinyVicky version in BCD (low)
|-
|0xD6AD
|CHV1
|TinyVicky version in BCD (high)
|-
|0xD6AE
|CHN0
|TinyVicky number in BCD (low)
|-
|0xD6AF
|CHN1
|TinyVicky number in BCD (high)
|-
|0xD6EB
|PCBMA
|PCB Major Rev (ASCII)
|-
|0xD6EC
|PCBMB
|PCB Minor Rev (ASCII)
|-
|0xD6ED
|PCBD
|PCB Day (BCD - Binary Coded Decimal)
|-
|0xD6EE
|PCBM
|PCB Month (BCD)
|-
|0xD6EF
|PCBY
|PCB Year (BCD)
|}

=== Special case of the F256K2 optical keyboard with a small LCD screen ===

Since the machine can lock up if you try to access the case-embedded LCD screen found (so far) only on the F256K2 with an optical keyboard, you must test a special bit in order to find whether it is an older style mechanical keyboard, or the newer style optical keyboard.
All K2 at release in 2025 and on have them, so for those, testing the machine MID code would be enough.
However, there are K2b boards released in late 2024 which were meant to give early access to the K2 machines, but they were meant to be temporarily used in the older F256K cases that have mechanical keyboards. Therefore, this following test must be performed to avoid locking up a machine that would attempt to access a non-present case embedded LCD.

Poll address 0xDDC1 and test bit 1 (second to last least significant bit).

If bit1 is set to 1 (ie 0bxxxxxx1x), the keyboard is mechanical and the embedded LCD is not available.

If bit1 is cleared to 0 (ie 0bxxxxxx0x), the keyboard is optical and the embedded LCD is available.

Hardware

2025-01-14T12:32:39Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!
F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2x SID (FPGA Emulation) 
1x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (Real) 
CODEC 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR1225 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:05:56Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2x SID (FPGA Emulation) 
1x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (Real) 
CODEC 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:04:13Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2x SID (FPGA Emulation) 
1x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (Real) 
CODEC 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:03:25Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2x SID (FPGA Emulation) 
1x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (Real) 
CODEC 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:02:50Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2x SID (FPGA Emulation) 
1x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (Real) 
CODEC 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
1 x OPL3 (FPGA Emulation) 
CODEC 
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:00:53Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|2 x PSG (FPGA Emulation)
2x SID (FPGA Emulation)

OPL3 (FPGA Emulation)

CODEC

PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T22:00:03Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|2 x PSG (FPGA Emulation)
2x SID (FPGA Emulation)

OPL3 (FPGA Emulation)

CODEC

PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T21:57:54Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|2 x PSG (FPGA Emulation)
2x SID (FPGA Emulation)

OPL3 (FPGA Emulation)

CODEC

PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T21:57:22Z

Foenix: /* Hardware Overview and Comparison */

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|2 x PSG (FPGA Emulation)
2x SID (FPGA Emulation)

OPL3 (FPGA Emulation)
CODEC,
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Hardware

2025-01-13T21:56:27Z

Foenix: Updating the JrJr Spec sheet

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
!F256Jr the 2nd ("Jr.Jr.")
! scope="row" style="text-align:left;" ; |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|onboard TQFP – WDC W65C816 CPU 
Motorola 6809 (optional FPGA configuration)
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S (included in the FPGA) 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|2MB SRAM (1Mx16) On Board (could be limited by Core) 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|TinyVicky II
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|2 x PSG (FPGA Emulation)
2x SID (FPGA Emulation)
OPL3 (FPGA Emulation)
CODEC,
PWM 
SAM2695 
VS1053b
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695 
VS1053b
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|1 x Micro HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Headphone 3.5mm 
1 x RCA Line Out (3.5mm) 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 5V through USB-C 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Through the Expansion Connector 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
2 x MIDI (1x in, 1x out) through the Expansion Connector
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output
|}

=== PS/2 Wiring Diagram for F256Jr ===
[[File:F256 Jr PS2 Wiring Diagram.png|left|thumb|PS/2 Wiring Diagram for F256Jr]]

Emulation

2024-12-28T01:17:51Z

Foenix: /* Installation */

=== '''FoenixIDE''' ===
The FoenixIDE provides emulation of various Foenix Retro Systems including,
{| class="wikitable"
|+
!System
!Descripton
|-
|F256K(816)
|The F256K computer with integrated keyboard and WDC65C816 processor.
|-
|F256K
|The F256K computer with integrated keyboard and WDC65C02 processor.
|-
|Jr(816)
|The F256 Jr. computer with a WDC65C816 processor.
|-
|Jr
|The F256 Jr. computer with a WDC65C02 processor.
|-
|U+
|The C256 Foenix U+ (4Meg RAM Config) - Legacy
|-
|U
|The C256 Foenix U (2Meg RAM Config) - Legacy
|-
|C
|The C256 Foenix FMX - Legacy
|-
|B
|The C256 Foenix (original) - Legacy
|}

=== '''Installation''' ===
The current Windows installation file (FoenixIDE.Setup.msi) and source code can be found here,
'''https://github.com/Trinity-11/FoenixIDE/releases'''

This is just a test for Captcha system

Use the VS1053b chip

2024-11-14T11:29:00Z

Foenix: Try to make things a bit cleater

Massive cleanup has to be done, code has to be tried.
Here's an info dump straight from discord

normally, let's assume we begin with a playback of a MP3, you read the file and you will need to dump like a 2K in before it tells you to stop. But, the FIFO inside the FPGA is also 2K, so in theory before things get ugly, you can upload in the MP3 playback system 2K+2K bytes, which ought to be enough to get it going. Now, if you monitor the FPGA FIFO info when empty you can put more in. Normally, after the VS1053 queue is full, it only need 32 bytes at the time and the FPGA takes care of that. Now, basically need to make sure the FPGA FIFO is topped off. Now, when come to end, you will need to fill extra bytes with 00 to empty the VS1053 Fifo and then the tune will end.

Now, the tricky parts is when one needs to stop the sound, there is also a process of filling the FIFO with 00 to cleanse the MP3 pipe. The specs talks about that.

This is as far as I went, now, I believe that if someone wants to play oggs and shit like that the controller need to be updated with new code since there are some issues in the latest tape out of the chip because remember people this is a DSP that actually can be programmed. There is actually an app note on how to use it to come out with Histogramic data (VUE bar app, with small LCD? anybody picking up on that? LOL) for one's pleasure

This is in a nutshell the process to playback stuff.
Here is the Register File Details for the VS1053 interface:

$D700..$D707

case( CPU_A_i[2:0] )
3'b000: begin CPU_D_o = {Busy, VS1053B_Registers[0][6:0]}; end
3'b001: begin CPU_D_o = VS1053B_Registers[1]; end
3'b010: begin CPU_D_o = VS1053B_Command_Read[7:0]; end
3'b011: begin CPU_D_o = VS1053B_Command_Read[15:8]; end
3'b100: begin CPU_D_o = Data_FIFO_Count[7:0]; end
3'b101: begin CPU_D_o = {VS1053B_FIFO_Empty, VS1053B_FIFO_Full, 3'b000, Data_FIFO_Count[10:8]}; end
3'b110: begin CPU_D_o = 8'h00; end
3'b111: begin CPU_D_o = 8'h00; end
endcase

'''VS1053B_Registers[0] - Bit Fields: ($D700..$D703)'''

[0] 1: Start Transfer

[1] 1: Read Register, 0: Write Register

[7] 1: SPI Transfer in Progress [Busy]

'''VS1053B_Registers[1]'''

[3:0] Register to Address

'''VS1053B_Registers[2] Data Access Low'''

'''VS1053B_Registers[3] Data Access Hi'''

There are 2 Accessible Area for the VS1053
The Control/Register Section with 16bits wide Data and 16 Addresses (See specs)
The Other is the Data(Stream) Port, there is no Address and it is 8bits

When one wants to control the chip, one need to setup the address and data (for write) and address for read, one needs to setup the direction and when everything is ready, one needs to trigger the transaction.
When one needs to write file data for playback, one needs only to write data to FIFO port @ $D704 and monitor FIFO @ $D705/$D706
Here is a piece of code, not the best, prolly not the most kosher either, but that ought to get you started.
I am simply playing back a very tiny sound effect (small enough to fit in the memory so not much to play back)

MP3_Playing:

lda #$42
sta $d702 ; Set the Stream mode
lda #$48
sta $d703
lda #$21 ; Start Transaction
sta $d700
lda #$20 ; Return to Zero
sta $d700

; lda #$00
; sta $d702
; sta $d703
; lda #$23 ; Go read the Command Register
; sta $d700
; lda $d702
; lda $d703

ldx #$00
VS_Pause:
inx
cpx #$80
bne VS_Pause

lda #$80
sta $00 ; Let's enable the MMU Edit, keep the MMU 00 in play
lda #$08 ; Bring about the first 8K
sta $0D ; It starts @ $08 == page 0

setaxl

ldx #$0000
ldy #$0000
; Go Fill the FIFO
setas
MP3_Fill_FIFO: ;lda @l MP3_Music,x
lda $A000,x
sta VS1053_STREAM_DATA ; THere is 2K FIFO
inx
iny
cpy #$0800 ; Fill 2K
bne MP3_Fill_FIFO

MP3_Fill_FIFO_Wait:
ldy #$0000
lda VS1053_FIFO_COUNT_HI ; Load High Portion is monitor for
and #$80
cmp #$80
bne MP3_Fill_FIFO_Wait

cpx #$2000
bne MP3_Fill_FIFO
ldx #$0000

lda $0D
inc A
sta $0D
cmp #$0c
bne MP3_Fill_FIFO

lda #$05
sta $0D
MP3_We_are_Done:
setaxs
rts

Template:Specs/F256K2

2024-10-25T04:05:46Z

Foenix:

[[File:F256K2 - Specs - OneSheeter RevB1.png|thumb|center|Spec Sheet for the F256K2]]

File:F256K2 - Specs - OneSheeter RevB1.png

2024-10-25T04:05:21Z

Foenix:

One Sheet Spec For the F256K2

Template:Specs/F256JR2

2024-10-25T04:01:53Z

Foenix:

[[File:F256JR2 - Specs - OneSheeter RevA.png|thumb|center|F256Jr.Jr. Spec Sheets]]

Template:Specs/F256JR2

2024-10-25T04:00:48Z

Foenix: Created page with "F256Jr.Jr. Spec Sheets"

[[File:F256JR2 - Specs - OneSheeter RevA.png|thumb|F256Jr.Jr. Spec Sheets]]

File:F256JR2 - Specs - OneSheeter RevA.png

2024-10-25T04:00:24Z

Foenix:

One Sheet Specifications for the Jr.Jr.

Product Specifications

2024-10-25T03:56:37Z

Foenix: Adding the Jr.Jr. In the lineup

{| style="width: 100%; margin: 0; padding: 0; border: 0; border-collapse: collapse;"
| style="padding: 0; width: 25%; vertical-align: top;" |


{{NocatBox|subject=F256 Jr.|page=Specs/F256Jr }}

| style="padding: 0 0 0 10px; width: 25%; vertical-align: top;" |


{{NocatBox|subject=F256K|page=Specs/F256K}}

| style="padding: 0 0 0 10px; width: 25%; vertical-align: top;" |


{{NocatBox|subject=F256K2|page=Specs/F256K2}}

| style="padding: 0 0 0 10px; width: 25%; vertical-align: top;" |


{{NocatBox|subject=F256JR2|page=Specs/F256JR2}}
|}

CartFlasher

2024-08-28T04:07:09Z

Foenix: Created page with "https://discord.com/channels/691915291721990194/1054250056703815680/1228540690691260416"

https://discord.com/channels/691915291721990194/1054250056703815680/1228540690691260416

Template:Main2/UtilitiesPage

2024-08-28T04:04:31Z

Foenix:

'''Utility Software'''
* [[F/Manager|f/Manager]]
* [[CartFlasher| Cartridge Flasher]]

Hardware

2024-08-05T09:04:18Z

Foenix:

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
! scope="row"; style="text-align:left;" |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM (DDR3 (64Mx16) 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (Digital TMDS) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore style IEC Port 
1 x Headphone 3.5mm 
1 x RCA Line Out 
1 x virtual Serial Port (USB-C (1 of 4 Channel)) 
1 x USB-C (1 of 4 Channel) Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Hardware

2024-08-05T09:01:55Z

Foenix:

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
! scope="row"; style="text-align:left;" |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (FPGA Emulation) 
2 x SID sockets (Real) 
|
2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (Real) 
CODEC 
|2 x PSG (FPGA Emulation) 
2 x SID (FPGA Emulation) 
OPL3 (FPGA Emulation) 
CODEC,
PWM 
SAM2695
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x virtual Serial Port (available over USB) 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Hardware

2024-08-05T08:59:34Z

Foenix: /* Hardware Overview and Comparison */ Updating details in the F256K2 column. Fix Typo

== Hardware Overview and Comparison ==
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
! scope="row"; style="text-align:left;" |
F256Jr
! scope="row"; style="text-align:left;" |
F256K
! scope="col"; style="text-align:left;" |
F256K2
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CPU
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
WDC W65C02S 
WDC W65C816S 
Foenix FNX6809 
|
 
WDC W65C816S 
Motorola 6809 (included in the FPGA) 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RAM
|
512 KB 
Optional 256K RAM expansion module available 
|
512 KB 
Optional 256K RAM expansion module available 
|
2MB SRAM (1Mx16) On Board (could be limited by Core) 
128 MB DRAM 
Optional 256K RAM expansion module available 
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Flash
|
512 KB 
Optional 256K Flash Modules 
|
512 KB 
Optional 256K Flash Modules 
|
512 KB Per Context (4x Contexts) 
Optional 256K Flash Modules 
|- style="vertical-align:top;"
! scope="col" style="text-align:left;" |
Graphic Chip
|
TinyVicky
|
TinyVicky
|
Vicky "The Fourth"
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Audio
|
2 x PSG (SN76489) 
2 x SID socket 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
|
2 x PSG 
2 x SID hardware emulation on board 
OPL3 
CODEC 
SAM2695

PWM
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
Connections
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
2 x Serial Port Pin-Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style Pin-Header 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x DVI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x Serial Port DB9M / 1 x Serial Pin Header 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
1 x SD Card Slot 
2 x Joystick Atari style DB9 Connector 
1 x Mini-DIN9 for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x JTAG Port for system updates (on bottom) 
1 x Wifi Module ESP32 Feather (internal) 
1 x Real Time Clock Battery CR2032 (internal) 
|
1 x HDMI (digital & analog) 
1 x PS2 (Mouse / External Keyboard) 
1 x Commodore syle IEC Port 
1 x Headphone 3.5 
1 x RCA Line Out 
1 x virtual Serial Port (available over USB) 
1 x Mini-USB Debug Port 
1 x Power 12V / 2A, 2,5mm Barrel Connector 
2 x SD Card Slot (1x internal, 1x external) 
2 x Joystick Atari style Pin-Header (1 Button + Analog) 
1 x PIN-Header onboard for SNES/NES Joystick Connector Box 
1 x Memory Expansion Slot (on Top) 
1 x Wifi (Wiznet with external antenna connector) 
1 x Real Time Clock Battery CR2032 (internal) 
1 x Ethernet (Wiznet Ethernet) 
2 x MIDI (1x in, 1x out) (optional) 
|}

== Hardware Details ==

=== CPU ===
The basic setup of all F256 is the [https://westerndesigncenter.com/ Western Design Center] '''65C02''', a slightly enhanced CMOS version of the very popular 6502 CPUs. The main difference to the 6502 in the 1970s and 1980s is the faster clock speed and the lower power consumption.

The 65C02 can also be replaced with a [[Template:Main2/65816 Processor|65816]] as a drop in replacement. '''Note, however, that while the 65c02 includes the additional Rockwell instructions (BBS/BBR, RMB/SMB), the 65816 does NOT. Therefore, these instructions should be avoided to ensure compatibility with F256 machines using the 65816.'''

In the F256, the CPU is always clocked at 6,29 MHz (6,293,750 Hz to be exact, derived from 25.175 MHz / 4 as discussed on [https://discord.com/channels/691915291721990194/1054250056703815680/1177306520925524018 Discord]).

=== Memory Expansion Slot ===
The memory expansion slot, located on the top right (above the keyboard), is intended primarily for Memory Expansion. It provides Address lines A0 - A17 (for addressing 256K), and active low Chip Select signal (CS_RAM) and Output Enable (OE) for the 256K Expansion address range $100000 - $13FFFF.

Foenix produce a 256K RAM Expansion cartridge, based on the CY7C1010DV33-10VXI, a high speed (10ns) 2Mbit (256K × 8) 3.3V Parallel Static RAM device.

The Expansion Slot itself, is based on a 36 pin PCI-Express x1 socket.

As the Expansion Slot also features pins for IRQ input, PHI2 clock output, and Reset (all signals which are unnecessary for a simple Memory interface), the Expansion Slot is also a candidate for other expansion purposes.

==== Utilizing the Expansion Slot (for your own purposes) ====

'''Warning:''' All signals on the Expansion Port are 3.3V logic level, therefore it is important that no voltage exceeding 3.3V is ever presented on any Expansion Port pin, or '''you risk damage''' to your F256!

If interfacing 5V TTL level devices to the Expansion Port, it is essential that level converters are used.

As an example, if directly interfacing to the Expansion Port pins with 5V logic, then you could use the SN74LVC8T245 bi-directional level translator, with the DIR input controlled by the Port's R/Wn signal (for the D0 - D7 bi-directional data bus), and the OEn input controlled by the Port's OEn signal. For the uni-directional Address and Control lines, the DIR input can be hardwired.

Note that the SN74LVC8T245 is designed so that the control pins (DIR and OE) are referenced to Vcca ('A' side voltage supplied). Therefore, a common practice would be to use side A for the internal (3.3V) side of the voltage translation, such that DIR and OE can be directly controlled by the Expansion Port's 3.3V level R/Wn and OEn pins. Side B (and Vccb) then being the 5V TTL level referenced (external facing) side.

As another example, if you were interfacing directly to a 3.3V peripheral chip (e.g. A W65C22 VIA powered by Vdd = 3.3V), but wanting to level translate to 5V TTL levels on the VIA's Port Pins, then an auto-direction level translator like the TI TXS010x series (TXS0108, TXS0104, TXS0101), might be more appropriate.

Note that on the TXS010x series the control pin (OE) is also referenced to Vcca ('A' side voltage supplied). With the TXS series, the 'A' side is actually limited to a 1.4V - 3.6V range, so is inherently the 3.3V internal side. Side 'B' is 1.65V - 5.5V, so is used for the external 5V TTL level referenced (external facing) side. So, if you're tying the active high OE pin of a TXS device (to permanently enable), it should be pulled to Vcca (not Vccb!).

==== Expansion Slot pin-out ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Side B
! scope="row"; style="text-align:left;" |
Side A
! scope="row"; style="text-align:left;" |
Signal
|- style="vertical-align:top;"
|
A4
! scope="col"; style="text-align:center;" |
B1
! scope="col"; style="text-align:center;" |
A1
|
nRST
|- style="vertical-align:top;"
|
A3
! scope="col"; style="text-align:center;" |
B2
! scope="col"; style="text-align:center;" |
A2
|
A5
|- style="vertical-align:top;"
|
A2
! scope="col"; style="text-align:center;" |
B3
! scope="col"; style="text-align:center;" |
A3
|
A6
|- style="vertical-align:top;"
|
A1
! scope="col"; style="text-align:center;" |
B4
! scope="col"; style="text-align:center;" |
A4
|
A7
|- style="vertical-align:top;"
|
A0
! scope="col"; style="text-align:center;" |
B5
! scope="col"; style="text-align:center;" |
A5
|
A8
|- style="vertical-align:top;"
|
CS_RAMn
! scope="col"; style="text-align:center;" |
B6
! scope="col"; style="text-align:center;" |
A6
|
OEn
|- style="vertical-align:top;"
|
D0
! scope="col"; style="text-align:center;" |
B7
! scope="col"; style="text-align:center;" |
A7
|
D7
|- style="vertical-align:top;"
|
D1
! scope="col"; style="text-align:center;" |
B8
! scope="col"; style="text-align:center;" |
A8
|
D6
|- style="vertical-align:top;"
|
3V3
! scope="col"; style="text-align:center;" |
B9
! scope="col"; style="text-align:center;" |
A9
|
GND
|- style="vertical-align:top;"
|
GND
! scope="col"; style="text-align:center;" |
B10
! scope="col"; style="text-align:center;" |
A10
|
3V3
|- style="vertical-align:top;"
|
D2
! scope="col"; style="text-align:center;" |
B11
! scope="col"; style="text-align:center;" |
A11
|
D5
|- style="vertical-align:top;"
! colspan="4"; scope="col"; style="text-align:center;" |
Key Notch
|- style="vertical-align:top;"
|
D3
! scope="col"; style="text-align:center;" |
B12
! scope="col"; style="text-align:center;" |
A12
|
D4
|- style="vertical-align:top;"
|
R/Wn
! scope="col"; style="text-align:center;" |
B13
! scope="col"; style="text-align:center;" |
A13
|
A9
|- style="vertical-align:top;"
|
A17
! scope="col"; style="text-align:center;" |
B14
! scope="col"; style="text-align:center;" |
A14
|
A10
|- style="vertical-align:top;"
|
A16
! scope="col"; style="text-align:center;" |
B15
! scope="col"; style="text-align:center;" |
A15
|
A11
|- style="vertical-align:top;"
|
A15
! scope="col"; style="text-align:center;" |
B16
! scope="col"; style="text-align:center;" |
A16
|
A12
|- style="vertical-align:top;"
|
A14
! scope="col"; style="text-align:center;" |
B17
! scope="col"; style="text-align:center;" |
A17
|
IRQn
|- style="vertical-align:top;"
|
A13
! scope="col"; style="text-align:center;" |
B18
! scope="col"; style="text-align:center;" |
A18
|
PHI2
|}

==== Expansion Slot - Signal Descriptions ====
{| class="wikitable"; style="text-align:left;"
|- style="vertical-align:top;"
! scope="row"; style="text-align:left;" |
Signal
! scope="row"; style="text-align:left;" |
Description
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
A0 - A17
|
Address Bus output (for addressing $100000 - $13FFFF Expansion space)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
D0 - D7
|
Data Bus (bi-directional)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
RSTn
|
Reset output (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
CS_RAMn
|
Chip Select output for Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
OEn
|
Output Enable output for a Read from Address Range $100000 - $13FFFF (active low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
3V3
|
3.3V Power output from the F256 (intended to power Expansion Interface only - '''Don't Exceed 500ma''')
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
GND
|
Digital Ground reference
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
R/Wn
|
Read/Write ouput (Read = high / Write = low)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
IRQn
|
Interrupt Request input - Internal pull-up and non-shared (compatible with open-drain or totem-pole driven)
|- style="vertical-align:top;"
! scope="col"; style="text-align:left;" |
PHI2
|
Phase 2 - Clock Output

Getting Started

2024-06-21T19:33:35Z

Foenix: /* Discord */ Invite links depracted

== Getting Powered Up ==

=== Powering your F256K ===

The F256K is powered via a standard 2.5mm DC Connector, which takes a centre-positive 12V 2A capable Power Supply.

This type of power supply is quite common. [https://www.amazon.com/Adapter-100-240V-Transformer-Charger-Security/dp/B091XSVV1Y Example 12V 2A capable power supply] (#)

(#) ''This specific power supply has not been verified (by the author) for use with the F256K. Please update this page with verified options!''

=== Powering your F256Jr ===

The F256Jr is supplied as a Mini-ITX form factor mainboard, with a standard 24 pin ATX power supply connector for power connectivity.

Since the F256Jr needs relatively little power, compared to a mini-ATX PC, a popular DC 12V 24pin Pico ATX PSU works well and is a compact solution.

* [https://www.amazon.com/dp/B08F57GKCL Pico PSU] - You power the Pico PSU via a 12V DC center-positive Power Supply source.
* [https://www.amazon.com/dp/B07MXXXBV8 12V DC center-positive A/C Adapter] - Commonly used to power the Pico PSU.
The board itself has no power switch. If you do not have a Mini-ITX case, a pin header on the board can be bridged by a jumper and thereby used instead of a proper power switch as a stop gap solution. In this picture https://wiki.c256foenix.com/images/6/64/Pinout_Jr_December_7th_Trans.png the pin header in question is shown in the lower right and is labeled with ''PW ON SPST Switch''.

== Getting programs onto the F256 ==

=== SD Card ===

Both the F256K and F256JR have an SD card slot. The device software to read the SD card is a bit touchy (it's inherited from the Commander X16 project) and doesn't work with all SD cards

* Cards should support the V2 protocol (HC or XC); older cards that only support the V1 protocol (typically 2GB or less) won't work. By contrast, the kernels for the C256 machines generally only work with V1 cards. Note that, in both cases, this is a software limitation -- all of the Foenix machines are electrically capable of using both kinds of cards.
* Cards *MUST* be formatted FAT32 -- **NOT: FAT, FAT12, FAT16, or exFAT**.
* Formatting with Windows 10/11 works fine, but make sure to force FAT32 (or use the command line: <code>format /FS:FAT32 H:</code>)
* Formatting with MacOS will only work using the <code>diskutil</code> command line utility. An example usage looks like this: <code>sudo diskutil eraseDisk FAT32 [DiskName] MBRFormat /dev/[DiskNumber]</code>. You can use <code>diskutil list</code> to get the disk number for the SD Card.
* Formatting and partitioning SD cards with Linux can be done using the <code>gnome-disk-utility</code> (known simply as Disks) and is installed on most mainstream distributions of Linux. Disks will access all the drives on the computer so be sure you have the SD card selected when editing. [https://wiki.gnome.org/Apps/Disks Gnome/Disks wiki]
* FAT32 only supports a maximum partition size of 32Gb, on larger cards you will need to create multiple partitions -- however, only the first is recognized by DOS.
* Some folks have had luck formatting cards with the [https://www.sdcard.org/downloads/formatter/sd-memory-card-formatter-for-windows-download/ Official SD Association formatter for Windows].

=== Demos Archive ===

* [https://github.com/FoenixRetro/Documentation/blob/main/f256/archive Download the most recent demos archive] and expand it to the root of the flash card.

=== Debug USB port ===

* This is what most developers use as it's the most convenient. Connect the debug USB port to your PC or Mac

* You can use:
** [https://github.com/pweingar/FoenixMgr FoenixMgr] - works on Windows, Mac, Linux
*** A Python script to manage the Foenix series of retro style computers through their USB debug ports. This tool allows uploading files of various formats to system RAM, and displaying memory through various means.

** [https://github.com/Trinity-11/FoenixIDE FoenixIDE] (Windows only)
*** Development and Debugging Suite for the C256 Foenix Family of Computers.

=== wget ===
If you have the [[wifi]] configured, you can use [https://github.com/ghackwrench/F256_wget wget] to pull programs and data right off the web!

== SuperBASIC ==

The machine boots to SuperBASIC. SuperBASIC is inspired by BBC BASIC but offers quite a bit more.

* Read the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual].

* Watch EMWhite's excellent intro series on Youtube:
** Full Playlist here: [https://www.youtube.com/playlist?list=PLeHjTvk7NPiSqGz4REMH-S4hjYpLS2YNR EMWhite's Intro Series - Full Playlist].
** Part 1 can be viewed here:
<youtube>G_S2c_MsqYA</youtube>

To get started, you can type in a sample program at the command prompt:

<pre>
10 for i=1 to 5
20 print "Hello world"
30 next
run
</pre>

SuperBASIC is similar to CBM (Microsoft) BASIC but has some differences. For example, note in the sample above it's just <code>next</code> not <code>next i</code>.

The first 15 or so pages of the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual] are quite instructive.

SuperBASIC is actually much more powerful and supports structured programming (procedures, blocks etc.)

<code>dir</code> - Run this to display directory of SD card

Loading & running programs off of the SD card is similarly easy:

<pre>
load "JrWordl.bas"
run
</pre>

Similar to the C64, you can save time in loading programs from the <code>dir</code> listing by using your cursor keys to go up to the entry, typing <code>load "</code> (insert mode is active by default) etc. You can use <code>CTRL+E</code> to jump to the end of the line and use <code>CTRL+K</code> to delete any text from the cursor to the end of the line. Correctly place the closing <code>"</code> and hit <code>ENTER</code>.

<code>CTRL+C</code> acts as a "break" command and stops any running SuperBASIC program or <code>LIST</code> command.

Read built-in help/reference:

<code>/help</code> : But '''NOTE''', this erases BASIC memory! Use Backspace key to go back in menus and to exit.

Explore the included demo SuperBASIC programs:

{| class="wikitable"
! Program !! Notes !! Source
|-
| <code>JrWordl.bas</code> || Wordle game, guess 5 letter word ||
|-
| <code>mandel.bas</code> || Draws Mandlebrot set in graphics mode, takes between 2 and 3 hours || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>rpg-demo.bas</code> || UI sample that shows Zelda like RPG game. Control the character with an Atari-joystick connected to JoyPort1 || @econtrerasd
|-
| <code>Problematic_Code.bas</code> || Displays scrolling starfield ||
|-
| <code>noelrl.bas</code> || Simple integer BASIC bench mark from Noel's retro lab. Completes < 3.5 seconds, compares very favourably to other retro systems! || [https://www.youtube.com/watch?v=H05hM_Guoqk Youtube]
|-
| <code>dance.bas</code> || Animates sprite of dancer || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>luna.bas</code> || Displays simple scene ||
|-
| <code>blink.bas</code> || Blinks drive access light || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>piano.bas</code> || Play some notes with the PSG || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|}

=== Running PGZ Files ===

<pre>
/- "file.pgz"
</pre>
=== More Resources ===
=== This Wiki ===

Explore all of the content of this Wiki, to expand your F256 series knowledge!

=== Discord ===

The [https://discord.gg/mUfNc3dQZj Foenix Retro Systems Discord] is the primary place to get questions answered.

Also, if you resolve your question, and you didn't find the answer here on the Wiki, '''''please consider contributing to the Wiki''''', for the benefit of others with the same question!

=== Foenix Retro Systems Newletter ===

Read back issues [http://apps.emwhite.org/foenixmarketplace/ here] (also a great source for sample programs).

Issues starting at #4 cover the F256 line. Issues 1-3 cover the previous version of the hardware (C256), although there are still many salient points.

Template:Specs/F256K2

2024-05-26T06:32:07Z

Foenix:

[[File:F256K2L - Specs - OneSheeter.png|thumb|center|F256K2_OneSheeter_Specification]]

Template:Specs/F256K2

2024-05-26T06:27:18Z

Foenix: Add F256K2 Specs

[[File:F256K2L - Specs - OneSheeter.png|thumb|F256K2_OneSheeter_Specification]]

File:F256K2L - Specs - OneSheeter.png

2024-05-26T06:26:56Z

Foenix:

Upcoming F256K2 General Specification

Product Specifications

2024-05-13T00:14:37Z

Foenix:

File Formats

2024-02-03T01:35:58Z

Foenix:

The F256 line has three file formats, each with slightly different properties and use cases. Additionally, pure binary files are often used by developers. The machine will be in a slightly different state, depending on how the program was started. We will cover this in the following sections.

== Binary ==
The binary file format is not a format as such. It is an image that is loaded directly into the F256's memory by a utility program running on the PC or Mac, and the F256 is then reset. Such an image must include properly initialized interrupt vectors, especially the RESET vector.

Running such an image requires knowledge of its starting address and a properly configured USB connection between the PC or Mac and the F256. Also, a jumper on the F256 Jr. motherboard must be moved to the "Boot-to-RAM" position. This is not necessary on the F256K.

Binary images should only be used by the developer while developing, as it is a very user-unfriendly method of distributing software, requiring tethering to a PC or Mac.

== KUP - Kernel User Program ==
KUPs are very simple and can contain 40 KiB code/data when run from flash, or 32 KiB when run from disk. Contained in their header is an entry point address, and the slot number of where they should be mapped into, the first possible slot being #1 ($2000).

DOS expands on the KUP header defined by the MicroKernel in a backwards compatible way.

The header is very simple:

<pre>
Byte 0 signature: $F2
Byte 1 signature: $56
Byte 2 the size of program in 8k blocks
Byte 3 the starting slot of the program (i.e. where to map it)
Bytes 4-5 the start address of the program
Byte 6 header structure version (indicates version of header, current 0 or 1)
Bytes 7-9 reserved
Bytes 10-? zero-terminated name of the program.
Bytes ?-? zero-terminated string describing the arguments. (in version >= 1)
Bytes ?-? zero-terminated string describing the program's function. (in version >= 1)
</pre>

Example of a header block definition:

<pre>
EXEC = __STARTUP_LOAD__
SLOT = __STARTUP_LOAD__ >> 13
COUNT = __END_LOAD__ >> 13 ; Assumes code starts at $2000.

.byte $f2,$56 ; signature
.byte <COUNT ; block count
.byte <SLOT ; start slot
.word EXEC ; exec addr
.byte 1 ; CHANGED, structure version
.byte 0 ; reserved
.byte 0 ; reserved
.byte 0 ; reserved
.asciiz "cwrite" ; name
.asciiz " "
.asciiz "App to program the Flash Cartridge"

.segment "END"
</pre>

The MicroKernel ignores the "argument" and "function" header entries. These are printed by DOS' <code>lsf</code> command, and only if the header version is greater or equal to 1.

When instructed to start a named KUP, the kernel will search through memory to find a match. First the expansion memory is searched, this could be either RAM or ROM. Then the on-board flash memory is searched. If DIP switch #1 is in the "on" position, the kernel will search memory banks 1-5 before the expansion blocks.

This sequence is also performed when the kernel starts up, for instance when the machine is reset or is first powered on.

Testing a KUP is therefore as easy as uploading it to a block of memory, and is an excellent choice for testing a program that interacts with the kernel. Though you should remember that this program will stay in memory as long as the machine is powered on, and may also survive a short power cut. Such a program should therefore, when testing, destroy its own header by overwriting the first two bytes with some values that are not the magic signature, to avoid being started again and again.

A KUP residing in flash does not "return" in the common sense of the word. If it has to terminate, it can either reset the machine, or use `RunNamed` to start another KUP.

On the other hand, when running a KUP from disk, it is able to return to DOS in a controlled manner. Distributing software intended to be run from disk as KUP is usually discouraged, as the program can only be started from DOS and not from SuperBASIC. It can, however, be appropriate for small utility programs mostly intended for maintenance tasks and so forth. When distributing software, you should prefer using one of the PGX or PGZ formats.

A KUP loaded from disk may exit back to DOS by issuing an RTS instruction. Additionally, the carry may be set if the machine should be reset, or carry clear to continue running DOS. Be aware that you must leave the MMU configuration in the state you found it for this to work properly. You should also keep away from the $0200-$07FF range completely.

When a KUP is started from flash, LUT #3 slots 0-5 is mapped to RAM banks 0-5, *except* where the KUP's header specifies where into should be mapped.

A KUP started from disk has LUT #3 slots 0-4 mapped to RAM, some of which will be the program itself.

In both cases the kernel is intact and available for use straight away.

== PGX ==
This format is a simple, single segment executable, which can be loaded as low as $0200. A PGX is loaded using <code>pexec</code>. <code>pexec</code> treats PGX and PGZ in exactly the same way, and information on how PGZ is handled also applies to PGX.

PGX is similar in scale to MS-DOS’s COM format, or the Commodore PRG format. It consists of a single segment of data to be loaded to
a specific address, where that address is also the starting address.

PGX starts with a header to identify the file and the starting address:

* The first three bytes are the ASCII codes for “PGX”.
* The fourth byte is the CPU and version identification byte. Bits 0 through 3 represent the CPU code, and bits 4 through 7 represent the version of PGX supported. At the moment, there is just version 0. The CPU code can be 1 for the WDC65816, or 3 for the 65c02.
* The next four bytes (that is, bytes 4 through 7) are the address of the destination, in little-endian format (least significant byte first). This address is both the address of the location in which to load the first byte of the data and is also the starting address for the file.

All bytes after the header are the contents of the file to be loaded into memory.

== PGZ ==
This is a more advanced multi-segment executable. It can be loaded as low as $0200. It is loaded using <code>pexec</code>.

When <code>pexec</code> loads a program, the program must not load itself into RAM banks 6 & 7, as these are used by the kernel, and the kernel is doing the actual loading. If the program does not need the kernel, it may of course utilize these banks once it is running. <code>pexec</code> is otherwise able to load code and data into anywhere in physical memory.

When the program starts, the state of the MMU LUTs is very similar to when a KUP starts. LUT #3 is active and slots 0-4 are mapped to RAM banks 0-4. The program's entry point must be in this region. Slots 6 and 7 are mapped to the kernel, which is intact and usable right away. Slot 5 is currently undefined.

Testing a PGZ can be done by using FoenixMgr and the <code>xdev</code> firmware component. It can of course also be copied to a disk or SD card, and manually run it on the machine.

A PGZ cannot "return" to another program, it can either start a KUP (if the kernel is intact) or reset the machine.

The first byte of the file is a file signature and also a version tag. If the first byte is an upper case Z, the file is a 24-bit PGZ file (i.e. all addresses and sizes specified in the file are 24-bits). If the file is a lower case Z, the file is a 32-bit PGZ file (all address and sizes are 32-bits in
length). Note that all addresses and sizes are in little endian format (that is, least significant
byte first).

After the initial byte, the remainder of the PGZ file consists of segments, one after the other. Each segment consists of two or three fields:

{| class="wikitable"
!Field!!Size!!Description
|-
|address||3 ('''Z''') or 4 ('''z''') bytes||The target address for this segment
|-
|size||3 ('''Z''') or 4 ('''z''') bytes||The number of bytes in the data field
|-
|data||'''size''' bytes||The data to be loaded (optional)
|}

For a particular segment, if the size field is 0, there will be no bytes in the data field, and the segment specifies the starting address of the entire program. At least one such segment must be present in the PGZ file for it to be executable. If more than one is present, the last one will
be the one used to specify the starting address.

 ''Original Information Source:'' https://github.com/FoenixRetro/Documentation/blob/main/f256/programming-file-formats.md

== PGZ (more details) ==

(More Complete Explanation ) - To be Re-Edited to form only one clear explanation of what the PGZ file format does. (This is the explanation coming from wiki.c256foenix.com)

PGZ is a multi-segment file format that can load data into multiple areas in memory. The format is derived from binary format used by Western Design Center's C compiler.

* The first byte of the PGZ format is the ASCII code for "Z". This serves as the file type signature.
* Big "Z" = 24bits Addresse Pointers and Sizes. Small "z" = 32bits Addresse Pointers and Sizes.
* Next comes any number of segments, each following right after the previous segment with no separator. Each segment has the following format:
** Three bytes of address, in little endian format. This is the starting address for writing the data of the segment.
** Three bytes indicating the size of the segment, in little endian format.
** The bytes of data in the segment (same number of bytes as specified in the size).
* If final segment has a size of $000000 and no data bytes, then address specifies the starting address of the executable.

{| class="wikitable"
! Segment !! Offset !! Count !! Example !! Purpose
|-
| N/A || 0 || 1 || "Z" || Signature
|-
|rowspan="3"| 1 || 1 || 3 || $010000 || Address of segment #1
|-
| 4 || 3 || $000009 || Size of segment #1
|-
| 7 || ... || ... || Data of Segment #1
|-
|rowspan="3"| 2 || 16 || 3 || $020000 || Address of segment #2
|-
| 19 || 3 || $000008 || Size of segment #2
|-
| 22 || ... || ... || Data of Segment #2
|-
|rowspan="2"| 3 || 30 || 3 || $010000 || Starting address
|-
| 33 || 3 || $000000 || 0 to indicate start address
|}

File Formats

2024-02-03T01:35:00Z

Foenix: /* PGZ */

The F256 line has three file formats, each with slightly different properties and use cases. Additionally, pure binary files are often used by developers. The machine will be in a slightly different state, depending on how the program was started. We will cover this in the following sections.

== Binary ==
The binary file format is not a format as such. It is an image that is loaded directly into the F256's memory by a utility program running on the PC or Mac, and the F256 is then reset. Such an image must include properly initialized interrupt vectors, especially the RESET vector.

Running such an image requires knowledge of its starting address and a properly configured USB connection between the PC or Mac and the F256. Also, a jumper on the F256 Jr. motherboard must be moved to the "Boot-to-RAM" position. This is not necessary on the F256K.

Binary images should only be used by the developer while developing, as it is a very user-unfriendly method of distributing software, requiring tethering to a PC or Mac.

== KUP - Kernel User Program ==
KUPs are very simple and can contain 40 KiB code/data when run from flash, or 32 KiB when run from disk. Contained in their header is an entry point address, and the slot number of where they should be mapped into, the first possible slot being #1 ($2000).

DOS expands on the KUP header defined by the MicroKernel in a backwards compatible way.

The header is very simple:

<pre>
Byte 0 signature: $F2
Byte 1 signature: $56
Byte 2 the size of program in 8k blocks
Byte 3 the starting slot of the program (i.e. where to map it)
Bytes 4-5 the start address of the program
Byte 6 header structure version (indicates version of header, current 0 or 1)
Bytes 7-9 reserved
Bytes 10-? zero-terminated name of the program.
Bytes ?-? zero-terminated string describing the arguments. (in version >= 1)
Bytes ?-? zero-terminated string describing the program's function. (in version >= 1)
</pre>

Example of a header block definition:

<pre>
EXEC = __STARTUP_LOAD__
SLOT = __STARTUP_LOAD__ >> 13
COUNT = __END_LOAD__ >> 13 ; Assumes code starts at $2000.

.byte $f2,$56 ; signature
.byte <COUNT ; block count
.byte <SLOT ; start slot
.word EXEC ; exec addr
.byte 1 ; CHANGED, structure version
.byte 0 ; reserved
.byte 0 ; reserved
.byte 0 ; reserved
.asciiz "cwrite" ; name
.asciiz " "
.asciiz "App to program the Flash Cartridge"

.segment "END"
</pre>

The MicroKernel ignores the "argument" and "function" header entries. These are printed by DOS' <code>lsf</code> command, and only if the header version is greater or equal to 1.

When instructed to start a named KUP, the kernel will search through memory to find a match. First the expansion memory is searched, this could be either RAM or ROM. Then the on-board flash memory is searched. If DIP switch #1 is in the "on" position, the kernel will search memory banks 1-5 before the expansion blocks.

This sequence is also performed when the kernel starts up, for instance when the machine is reset or is first powered on.

Testing a KUP is therefore as easy as uploading it to a block of memory, and is an excellent choice for testing a program that interacts with the kernel. Though you should remember that this program will stay in memory as long as the machine is powered on, and may also survive a short power cut. Such a program should therefore, when testing, destroy its own header by overwriting the first two bytes with some values that are not the magic signature, to avoid being started again and again.

A KUP residing in flash does not "return" in the common sense of the word. If it has to terminate, it can either reset the machine, or use `RunNamed` to start another KUP.

On the other hand, when running a KUP from disk, it is able to return to DOS in a controlled manner. Distributing software intended to be run from disk as KUP is usually discouraged, as the program can only be started from DOS and not from SuperBASIC. It can, however, be appropriate for small utility programs mostly intended for maintenance tasks and so forth. When distributing software, you should prefer using one of the PGX or PGZ formats.

A KUP loaded from disk may exit back to DOS by issuing an RTS instruction. Additionally, the carry may be set if the machine should be reset, or carry clear to continue running DOS. Be aware that you must leave the MMU configuration in the state you found it for this to work properly. You should also keep away from the $0200-$07FF range completely.

When a KUP is started from flash, LUT #3 slots 0-5 is mapped to RAM banks 0-5, *except* where the KUP's header specifies where into should be mapped.

A KUP started from disk has LUT #3 slots 0-4 mapped to RAM, some of which will be the program itself.

In both cases the kernel is intact and available for use straight away.

== PGX ==
This format is a simple, single segment executable, which can be loaded as low as $0200. A PGX is loaded using <code>pexec</code>. <code>pexec</code> treats PGX and PGZ in exactly the same way, and information on how PGZ is handled also applies to PGX.

PGX is similar in scale to MS-DOS’s COM format, or the Commodore PRG format. It consists of a single segment of data to be loaded to
a specific address, where that address is also the starting address.

PGX starts with a header to identify the file and the starting address:

* The first three bytes are the ASCII codes for “PGX”.
* The fourth byte is the CPU and version identification byte. Bits 0 through 3 represent the CPU code, and bits 4 through 7 represent the version of PGX supported. At the moment, there is just version 0. The CPU code can be 1 for the WDC65816, or 3 for the 65c02.
* The next four bytes (that is, bytes 4 through 7) are the address of the destination, in little-endian format (least significant byte first). This address is both the address of the location in which to load the first byte of the data and is also the starting address for the file.

All bytes after the header are the contents of the file to be loaded into memory.

== PGZ ==
This is a more advanced multi-segment executable. It can be loaded as low as $0200. It is loaded using <code>pexec</code>.

When <code>pexec</code> loads a program, the program must not load itself into RAM banks 6 & 7, as these are used by the kernel, and the kernel is doing the actual loading. If the program does not need the kernel, it may of course utilize these banks once it is running. <code>pexec</code> is otherwise able to load code and data into anywhere in physical memory.

When the program starts, the state of the MMU LUTs is very similar to when a KUP starts. LUT #3 is active and slots 0-4 are mapped to RAM banks 0-4. The program's entry point must be in this region. Slots 6 and 7 are mapped to the kernel, which is intact and usable right away. Slot 5 is currently undefined.

Testing a PGZ can be done by using FoenixMgr and the <code>xdev</code> firmware component. It can of course also be copied to a disk or SD card, and manually run it on the machine.

A PGZ cannot "return" to another program, it can either start a KUP (if the kernel is intact) or reset the machine.

The first byte of the file is a file signature and also a version tag. If the first byte is an upper case Z, the file is a 24-bit PGZ file (i.e. all addresses and sizes specified in the file are 24-bits). If the file is a lower case Z, the file is a 32-bit PGZ file (all address and sizes are 32-bits in
length). Note that all addresses and sizes are in little endian format (that is, least significant
byte first).

After the initial byte, the remainder of the PGZ file consists of segments, one after the other. Each segment consists of two or three fields:

{| class="wikitable"
!Field!!Size!!Description
|-
|address||3 ('''Z''') or 4 ('''z''') bytes||The target address for this segment
|-
|size||3 ('''Z''') or 4 ('''z''') bytes||The number of bytes in the data field
|-
|data||'''size''' bytes||The data to be loaded (optional)
|}

For a particular segment, if the size field is 0, there will be no bytes in the data field, and the segment specifies the starting address of the entire program. At least one such segment must be present in the PGZ file for it to be executable. If more than one is present, the last one will
be the one used to specify the starting address.

 ''Original Information Source:'' https://github.com/FoenixRetro/Documentation/blob/main/f256/programming-file-formats.md

<nowiki>== PGZ ==</nowiki>

(More Complete Explanation ) - To be Re-Edited to form only one clear explanation of what the PGZ file format does. (This is the explanation coming from wiki.c256foenix.com)

PGZ is a multi-segment file format that can load data into multiple areas in memory. The format is derived from binary format used by Western Design Center's C compiler.

* The first byte of the PGZ format is the ASCII code for "Z". This serves as the file type signature.
* Big "Z" = 24bits Addresse Pointers and Sizes. Small "z" = 32bits Addresse Pointers and Sizes.
* Next comes any number of segments, each following right after the previous segment with no separator. Each segment has the following format:
** Three bytes of address, in little endian format. This is the starting address for writing the data of the segment.
** Three bytes indicating the size of the segment, in little endian format.
** The bytes of data in the segment (same number of bytes as specified in the size).
* If final segment has a size of $000000 and no data bytes, then address specifies the starting address of the executable.

{| class="wikitable"
! Segment !! Offset !! Count !! Example !! Purpose
|-
| N/A || 0 || 1 || "Z" || Signature
|-
|rowspan="3"| 1 || 1 || 3 || $010000 || Address of segment #1
|-
| 4 || 3 || $000009 || Size of segment #1
|-
| 7 || ... || ... || Data of Segment #1
|-
|rowspan="3"| 2 || 16 || 3 || $020000 || Address of segment #2
|-
| 19 || 3 || $000008 || Size of segment #2
|-
| 22 || ... || ... || Data of Segment #2
|-
|rowspan="2"| 3 || 30 || 3 || $010000 || Starting address
|-
| 33 || 3 || $000000 || 0 to indicate start address
|}

File Formats

2024-02-03T01:34:33Z

Foenix: /* PGZ */

The F256 line has three file formats, each with slightly different properties and use cases. Additionally, pure binary files are often used by developers. The machine will be in a slightly different state, depending on how the program was started. We will cover this in the following sections.

== Binary ==
The binary file format is not a format as such. It is an image that is loaded directly into the F256's memory by a utility program running on the PC or Mac, and the F256 is then reset. Such an image must include properly initialized interrupt vectors, especially the RESET vector.

Running such an image requires knowledge of its starting address and a properly configured USB connection between the PC or Mac and the F256. Also, a jumper on the F256 Jr. motherboard must be moved to the "Boot-to-RAM" position. This is not necessary on the F256K.

Binary images should only be used by the developer while developing, as it is a very user-unfriendly method of distributing software, requiring tethering to a PC or Mac.

== KUP - Kernel User Program ==
KUPs are very simple and can contain 40 KiB code/data when run from flash, or 32 KiB when run from disk. Contained in their header is an entry point address, and the slot number of where they should be mapped into, the first possible slot being #1 ($2000).

DOS expands on the KUP header defined by the MicroKernel in a backwards compatible way.

The header is very simple:

<pre>
Byte 0 signature: $F2
Byte 1 signature: $56
Byte 2 the size of program in 8k blocks
Byte 3 the starting slot of the program (i.e. where to map it)
Bytes 4-5 the start address of the program
Byte 6 header structure version (indicates version of header, current 0 or 1)
Bytes 7-9 reserved
Bytes 10-? zero-terminated name of the program.
Bytes ?-? zero-terminated string describing the arguments. (in version >= 1)
Bytes ?-? zero-terminated string describing the program's function. (in version >= 1)
</pre>

Example of a header block definition:

<pre>
EXEC = __STARTUP_LOAD__
SLOT = __STARTUP_LOAD__ >> 13
COUNT = __END_LOAD__ >> 13 ; Assumes code starts at $2000.

.byte $f2,$56 ; signature
.byte <COUNT ; block count
.byte <SLOT ; start slot
.word EXEC ; exec addr
.byte 1 ; CHANGED, structure version
.byte 0 ; reserved
.byte 0 ; reserved
.byte 0 ; reserved
.asciiz "cwrite" ; name
.asciiz " "
.asciiz "App to program the Flash Cartridge"

.segment "END"
</pre>

The MicroKernel ignores the "argument" and "function" header entries. These are printed by DOS' <code>lsf</code> command, and only if the header version is greater or equal to 1.

When instructed to start a named KUP, the kernel will search through memory to find a match. First the expansion memory is searched, this could be either RAM or ROM. Then the on-board flash memory is searched. If DIP switch #1 is in the "on" position, the kernel will search memory banks 1-5 before the expansion blocks.

This sequence is also performed when the kernel starts up, for instance when the machine is reset or is first powered on.

Testing a KUP is therefore as easy as uploading it to a block of memory, and is an excellent choice for testing a program that interacts with the kernel. Though you should remember that this program will stay in memory as long as the machine is powered on, and may also survive a short power cut. Such a program should therefore, when testing, destroy its own header by overwriting the first two bytes with some values that are not the magic signature, to avoid being started again and again.

A KUP residing in flash does not "return" in the common sense of the word. If it has to terminate, it can either reset the machine, or use `RunNamed` to start another KUP.

On the other hand, when running a KUP from disk, it is able to return to DOS in a controlled manner. Distributing software intended to be run from disk as KUP is usually discouraged, as the program can only be started from DOS and not from SuperBASIC. It can, however, be appropriate for small utility programs mostly intended for maintenance tasks and so forth. When distributing software, you should prefer using one of the PGX or PGZ formats.

A KUP loaded from disk may exit back to DOS by issuing an RTS instruction. Additionally, the carry may be set if the machine should be reset, or carry clear to continue running DOS. Be aware that you must leave the MMU configuration in the state you found it for this to work properly. You should also keep away from the $0200-$07FF range completely.

When a KUP is started from flash, LUT #3 slots 0-5 is mapped to RAM banks 0-5, *except* where the KUP's header specifies where into should be mapped.

A KUP started from disk has LUT #3 slots 0-4 mapped to RAM, some of which will be the program itself.

In both cases the kernel is intact and available for use straight away.

== PGX ==
This format is a simple, single segment executable, which can be loaded as low as $0200. A PGX is loaded using <code>pexec</code>. <code>pexec</code> treats PGX and PGZ in exactly the same way, and information on how PGZ is handled also applies to PGX.

PGX is similar in scale to MS-DOS’s COM format, or the Commodore PRG format. It consists of a single segment of data to be loaded to
a specific address, where that address is also the starting address.

PGX starts with a header to identify the file and the starting address:

* The first three bytes are the ASCII codes for “PGX”.
* The fourth byte is the CPU and version identification byte. Bits 0 through 3 represent the CPU code, and bits 4 through 7 represent the version of PGX supported. At the moment, there is just version 0. The CPU code can be 1 for the WDC65816, or 3 for the 65c02.
* The next four bytes (that is, bytes 4 through 7) are the address of the destination, in little-endian format (least significant byte first). This address is both the address of the location in which to load the first byte of the data and is also the starting address for the file.

All bytes after the header are the contents of the file to be loaded into memory.

== PGZ ==
This is a more advanced multi-segment executable. It can be loaded as low as $0200. It is loaded using <code>pexec</code>.

When <code>pexec</code> loads a program, the program must not load itself into RAM banks 6 & 7, as these are used by the kernel, and the kernel is doing the actual loading. If the program does not need the kernel, it may of course utilize these banks once it is running. <code>pexec</code> is otherwise able to load code and data into anywhere in physical memory.

When the program starts, the state of the MMU LUTs is very similar to when a KUP starts. LUT #3 is active and slots 0-4 are mapped to RAM banks 0-4. The program's entry point must be in this region. Slots 6 and 7 are mapped to the kernel, which is intact and usable right away. Slot 5 is currently undefined.

Testing a PGZ can be done by using FoenixMgr and the <code>xdev</code> firmware component. It can of course also be copied to a disk or SD card, and manually run it on the machine.

A PGZ cannot "return" to another program, it can either start a KUP (if the kernel is intact) or reset the machine.

The first byte of the file is a file signature and also a version tag. If the first byte is an upper case Z, the file is a 24-bit PGZ file (i.e. all addresses and sizes specified in the file are 24-bits). If the file is a lower case Z, the file is a 32-bit PGZ file (all address and sizes are 32-bits in
length). Note that all addresses and sizes are in little endian format (that is, least significant
byte first).

After the initial byte, the remainder of the PGZ file consists of segments, one after the other. Each segment consists of two or three fields:

{| class="wikitable"
!Field!!Size!!Description
|-
|address||3 ('''Z''') or 4 ('''z''') bytes||The target address for this segment
|-
|size||3 ('''Z''') or 4 ('''z''') bytes||The number of bytes in the data field
|-
|data||'''size''' bytes||The data to be loaded (optional)
|}

For a particular segment, if the size field is 0, there will be no bytes in the data field, and the segment specifies the starting address of the entire program. At least one such segment must be present in the PGZ file for it to be executable. If more than one is present, the last one will
be the one used to specify the starting address.

 ''Original Information Source:'' https://github.com/FoenixRetro/Documentation/blob/main/f256/programming-file-formats.md

<nowiki>== PGZ (better explanation) ==</nowiki>

(More Complete Explanation ) - To be Re-Edited to form only one clear explanation of what the PGZ file format does. (This is the explanation coming from wiki.c256foenix.com)

PGZ is a multi-segment file format that can load data into multiple areas in memory. The format is derived from binary format used by Western Design Center's C compiler.

* The first byte of the PGZ format is the ASCII code for "Z". This serves as the file type signature.
* Big "Z" = 24bits Addresse Pointers and Sizes. Small "z" = 32bits Addresse Pointers and Sizes.
* Next comes any number of segments, each following right after the previous segment with no separator. Each segment has the following format:
** Three bytes of address, in little endian format. This is the starting address for writing the data of the segment.
** Three bytes indicating the size of the segment, in little endian format.
** The bytes of data in the segment (same number of bytes as specified in the size).
* If final segment has a size of $000000 and no data bytes, then address specifies the starting address of the executable.

{| class="wikitable"
! Segment !! Offset !! Count !! Example !! Purpose
|-
| N/A || 0 || 1 || "Z" || Signature
|-
|rowspan="3"| 1 || 1 || 3 || $010000 || Address of segment #1
|-
| 4 || 3 || $000009 || Size of segment #1
|-
| 7 || ... || ... || Data of Segment #1
|-
|rowspan="3"| 2 || 16 || 3 || $020000 || Address of segment #2
|-
| 19 || 3 || $000008 || Size of segment #2
|-
| 22 || ... || ... || Data of Segment #2
|-
|rowspan="2"| 3 || 30 || 3 || $010000 || Starting address
|-
| 33 || 3 || $000000 || 0 to indicate start address
|}

File Formats

2024-02-03T01:33:52Z

Foenix: /* PGZ */

The F256 line has three file formats, each with slightly different properties and use cases. Additionally, pure binary files are often used by developers. The machine will be in a slightly different state, depending on how the program was started. We will cover this in the following sections.

== Binary ==
The binary file format is not a format as such. It is an image that is loaded directly into the F256's memory by a utility program running on the PC or Mac, and the F256 is then reset. Such an image must include properly initialized interrupt vectors, especially the RESET vector.

Running such an image requires knowledge of its starting address and a properly configured USB connection between the PC or Mac and the F256. Also, a jumper on the F256 Jr. motherboard must be moved to the "Boot-to-RAM" position. This is not necessary on the F256K.

Binary images should only be used by the developer while developing, as it is a very user-unfriendly method of distributing software, requiring tethering to a PC or Mac.

== KUP - Kernel User Program ==
KUPs are very simple and can contain 40 KiB code/data when run from flash, or 32 KiB when run from disk. Contained in their header is an entry point address, and the slot number of where they should be mapped into, the first possible slot being #1 ($2000).

DOS expands on the KUP header defined by the MicroKernel in a backwards compatible way.

The header is very simple:

<pre>
Byte 0 signature: $F2
Byte 1 signature: $56
Byte 2 the size of program in 8k blocks
Byte 3 the starting slot of the program (i.e. where to map it)
Bytes 4-5 the start address of the program
Byte 6 header structure version (indicates version of header, current 0 or 1)
Bytes 7-9 reserved
Bytes 10-? zero-terminated name of the program.
Bytes ?-? zero-terminated string describing the arguments. (in version >= 1)
Bytes ?-? zero-terminated string describing the program's function. (in version >= 1)
</pre>

Example of a header block definition:

<pre>
EXEC = __STARTUP_LOAD__
SLOT = __STARTUP_LOAD__ >> 13
COUNT = __END_LOAD__ >> 13 ; Assumes code starts at $2000.

.byte $f2,$56 ; signature
.byte <COUNT ; block count
.byte <SLOT ; start slot
.word EXEC ; exec addr
.byte 1 ; CHANGED, structure version
.byte 0 ; reserved
.byte 0 ; reserved
.byte 0 ; reserved
.asciiz "cwrite" ; name
.asciiz " "
.asciiz "App to program the Flash Cartridge"

.segment "END"
</pre>

The MicroKernel ignores the "argument" and "function" header entries. These are printed by DOS' <code>lsf</code> command, and only if the header version is greater or equal to 1.

When instructed to start a named KUP, the kernel will search through memory to find a match. First the expansion memory is searched, this could be either RAM or ROM. Then the on-board flash memory is searched. If DIP switch #1 is in the "on" position, the kernel will search memory banks 1-5 before the expansion blocks.

This sequence is also performed when the kernel starts up, for instance when the machine is reset or is first powered on.

Testing a KUP is therefore as easy as uploading it to a block of memory, and is an excellent choice for testing a program that interacts with the kernel. Though you should remember that this program will stay in memory as long as the machine is powered on, and may also survive a short power cut. Such a program should therefore, when testing, destroy its own header by overwriting the first two bytes with some values that are not the magic signature, to avoid being started again and again.

A KUP residing in flash does not "return" in the common sense of the word. If it has to terminate, it can either reset the machine, or use `RunNamed` to start another KUP.

On the other hand, when running a KUP from disk, it is able to return to DOS in a controlled manner. Distributing software intended to be run from disk as KUP is usually discouraged, as the program can only be started from DOS and not from SuperBASIC. It can, however, be appropriate for small utility programs mostly intended for maintenance tasks and so forth. When distributing software, you should prefer using one of the PGX or PGZ formats.

A KUP loaded from disk may exit back to DOS by issuing an RTS instruction. Additionally, the carry may be set if the machine should be reset, or carry clear to continue running DOS. Be aware that you must leave the MMU configuration in the state you found it for this to work properly. You should also keep away from the $0200-$07FF range completely.

When a KUP is started from flash, LUT #3 slots 0-5 is mapped to RAM banks 0-5, *except* where the KUP's header specifies where into should be mapped.

A KUP started from disk has LUT #3 slots 0-4 mapped to RAM, some of which will be the program itself.

In both cases the kernel is intact and available for use straight away.

== PGX ==
This format is a simple, single segment executable, which can be loaded as low as $0200. A PGX is loaded using <code>pexec</code>. <code>pexec</code> treats PGX and PGZ in exactly the same way, and information on how PGZ is handled also applies to PGX.

PGX is similar in scale to MS-DOS’s COM format, or the Commodore PRG format. It consists of a single segment of data to be loaded to
a specific address, where that address is also the starting address.

PGX starts with a header to identify the file and the starting address:

* The first three bytes are the ASCII codes for “PGX”.
* The fourth byte is the CPU and version identification byte. Bits 0 through 3 represent the CPU code, and bits 4 through 7 represent the version of PGX supported. At the moment, there is just version 0. The CPU code can be 1 for the WDC65816, or 3 for the 65c02.
* The next four bytes (that is, bytes 4 through 7) are the address of the destination, in little-endian format (least significant byte first). This address is both the address of the location in which to load the first byte of the data and is also the starting address for the file.

All bytes after the header are the contents of the file to be loaded into memory.

== PGZ ==
This is a more advanced multi-segment executable. It can be loaded as low as $0200. It is loaded using <code>pexec</code>.

When <code>pexec</code> loads a program, the program must not load itself into RAM banks 6 & 7, as these are used by the kernel, and the kernel is doing the actual loading. If the program does not need the kernel, it may of course utilize these banks once it is running. <code>pexec</code> is otherwise able to load code and data into anywhere in physical memory.

When the program starts, the state of the MMU LUTs is very similar to when a KUP starts. LUT #3 is active and slots 0-4 are mapped to RAM banks 0-4. The program's entry point must be in this region. Slots 6 and 7 are mapped to the kernel, which is intact and usable right away. Slot 5 is currently undefined.

Testing a PGZ can be done by using FoenixMgr and the <code>xdev</code> firmware component. It can of course also be copied to a disk or SD card, and manually run it on the machine.

A PGZ cannot "return" to another program, it can either start a KUP (if the kernel is intact) or reset the machine.

The first byte of the file is a file signature and also a version tag. If the first byte is an upper case Z, the file is a 24-bit PGZ file (i.e. all addresses and sizes specified in the file are 24-bits). If the file is a lower case Z, the file is a 32-bit PGZ file (all address and sizes are 32-bits in
length). Note that all addresses and sizes are in little endian format (that is, least significant
byte first).

After the initial byte, the remainder of the PGZ file consists of segments, one after the other. Each segment consists of two or three fields:

{| class="wikitable"
!Field!!Size!!Description
|-
|address||3 ('''Z''') or 4 ('''z''') bytes||The target address for this segment
|-
|size||3 ('''Z''') or 4 ('''z''') bytes||The number of bytes in the data field
|-
|data||'''size''' bytes||The data to be loaded (optional)
|}

For a particular segment, if the size field is 0, there will be no bytes in the data field, and the segment specifies the starting address of the entire program. At least one such segment must be present in the PGZ file for it to be executable. If more than one is present, the last one will
be the one used to specify the starting address.

 ''Original Information Source:'' https://github.com/FoenixRetro/Documentation/blob/main/f256/programming-file-formats.md

== PGZ == (More Complete Explanation ) - To be Re-Edited to form only one clear explanation of what the PGZ file format does. (This is the explanation coming from wiki.c256foenix.com)

PGZ is a multi-segment file format that can load data into multiple areas in memory. The format is derived from binary format used by Western Design Center's C compiler.

* The first byte of the PGZ format is the ASCII code for "Z". This serves as the file type signature.
* Big "Z" = 24bits Addresse Pointers and Sizes. Small "z" = 32bits Addresse Pointers and Sizes.
* Next comes any number of segments, each following right after the previous segment with no separator. Each segment has the following format:
** Three bytes of address, in little endian format. This is the starting address for writing the data of the segment.
** Three bytes indicating the size of the segment, in little endian format.
** The bytes of data in the segment (same number of bytes as specified in the size).
* If final segment has a size of $000000 and no data bytes, then address specifies the starting address of the executable.

{| class="wikitable"
! Segment !! Offset !! Count !! Example !! Purpose
|-
| N/A || 0 || 1 || "Z" || Signature
|-
|rowspan="3"| 1 || 1 || 3 || $010000 || Address of segment #1
|-
| 4 || 3 || $000009 || Size of segment #1
|-
| 7 || ... || ... || Data of Segment #1
|-
|rowspan="3"| 2 || 16 || 3 || $020000 || Address of segment #2
|-
| 19 || 3 || $000008 || Size of segment #2
|-
| 22 || ... || ... || Data of Segment #2
|-
|rowspan="2"| 3 || 30 || 3 || $010000 || Starting address
|-
| 33 || 3 || $000000 || 0 to indicate start address
|}

Tools & Scripts

2024-01-21T00:15:28Z

Foenix: Page creation to assemble the tools & scripts to create Sprite and Tilemaps

== F256 Machines Game Development Tools ==

=== Sprite Creation Tools & Scripts ===

{| class="wikitable"
! Tool !! Link
! --- !! Notes
|-
| style="white-space:nowrap;"| Aseprite
| style="white-space:nowrap;"| https://www.aseprite.org/
|
| style="white-space:nowrap;" |Aseprite can be used to create sprites animation or Tiles Sets.
|}

==== Scripts ====

=== Tile Creation Tools & Scripts ===

Template:Main2/Game Development

2024-01-21T00:04:47Z

Foenix: Created page with "'''Game Development''' * Tools & Scripts"

'''Game Development'''
* [[Tools & Scripts]]

Main Page

2024-01-21T00:02:02Z

Foenix:

<div id="mainpage"></div> __NOTOC__ __NOEDITSECTION__


<div style="margin: 0 0 15px 0; padding: 1px; border: 1px solid #CCCCCC;">
{| style="width: 100%; margin: 0; padding: 0; border: 0; background-color: #FCFCFC; color: #000000; border-collapse: collapse;"
| align="center" style="vertical-align: top;"|
<div style="font-size: 150%;">Welcome to the Foenix Retro Systems' F256x series Wiki</div>
<div style="font-size: 100%; margin-top: 0.7em; line-height: 130%;">Dedicated to the WDC65C02/WDC65C816 or FNX6809 based F256x series.</div>
|}
</div>


{| style="width: 100%; margin: 0; padding: 0; border: 0; border-collapse: collapse;"
| style="padding: 0; width: 25%; vertical-align: top;" |


{{NocatBox|subject=Getting Started|page=Main2/Getting_Started}}
{{NocatBox|subject=Technical Overview|page=Main2/Technical_Overview}}
{{NocatBox|subject=System Maintenance|page=Main2/System_Maintenance}}

| style="padding: 0 0 0 10px; width: 25%; vertical-align: top;" |


{{NocatBox|subject=Software Development|page=Main2/Software_Development}}
{{NocatBox|subject=W65C816 Processor|page=Main2/65816_Processor}}
{{NocatBox|subject=FNX6809 Processor|page=Main2/FNX6809_Processor}}
{{NocatBox|subject=Game Development|page=Main2/Game_Development}}
|}

FPGA Releases

2023-12-31T10:34:09Z

Foenix: /* Current F256Jr Release */

== F256K FPGA Releases ==

=== Current F256K Release ===

{| class="wikitable"
! Series !! Version
!Code!! Date !! Download !! Release Notes
|-
| style="white-space:nowrap;"| F256K
| style="white-space:nowrap;"| Release Candidate 14
|00140000 B0
| style="white-space:nowrap;" | 23-Dec-2023
| style="white-space:nowrap;" | [https://ptb.discord.com/channels/691915291721990194/1054250189675843736/1188628633502359602 F256K_WBh_Dec23rd_RevB0x_RC14_0000.jic]
|Fixes a problem with the tiles; needed to be shifted by one towards the left.
|}

=== Previous F256K Releases ===

{| class="wikitable"
! Series !! Version
!Code!! Date !! Download !! Release Notes
|-
|F256K
|Release Candidate 13
|00130000 B0
|09-Dec-2023
|[https://cdn.discordapp.com/attachments/1054250189675843736/1182993744044249149/F256K_WBh_Dec9th_RevB0x_RC13_0000.jic F256K_WBh_Dec9th_RevB0x_RC13_0000.jic]
|
* Fixes a problem with Interrupt from timer0 that was working on the Jr.
* Resolves a discrepancy between the F256Jr interrupt block and the F256K.
|-
| style="white-space:nowrap;"| F256K
| style="white-space:nowrap;"| Release Candidate 12
|00120011 B0
| style="white-space:nowrap;" | 19-Nov-2023
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1054250189675843736/1175965530000212048/F256K_WBh_Nov19th_RevB0x_RC12_0011.jic F256K_WBh_Nov19th_RevB0x_RC12_0011.jic]
|
Corrects the issue with no-response from command $20 & $21 (not being processed in the early parser).
The Jr doesn't have the issue.
|}

== F256Jr FPGA Releases ==

=== Current F256Jr Release ===

{| class="wikitable"
! Series !! Version
!Code!! Date !! Download !! Release Notes
|-
| style="white-space:nowrap;"| F256Jr
| style="white-space:nowrap;"| Release Candidate 18
|00180100 B0
| style="white-space:nowrap;" | 23-Dec-2023
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1188629310081347584/F256M_Wbh_Dec23rd_2023_RC18_0100.jic?ex=659b384f&is=6588c34f&hm=e38627d1334595c2bae737ba996c398b5d748a979624b79005cb720664453111& F256M_Wbh_Dec23rd_2023_RC18_0100.jic]
|Fixes a problem with the tiles; needed to be shifted by one towards the left. (0100 = Serial RAM/Flash Select)
|}

=== Previous F256Jr Releases ===

{| class="wikitable"
! Series !! Version
!Code!! Date !! Download !! Release Notes
|-
|F256Jr
|Release Candidate 17
|?
|18-Nov-2023
|[https://cdn.discordapp.com/attachments/1010352563406770217/1175321652859523123/F256M_Wbh_Nov18th_2023_RC17_0100.jic F256M_Wbh_Nov18th_2023_RC17_0100.jic]
|In light of decision to dump the big ticket items and the accessories from the store...
* Removed the very SPI core introduced yesterday to drive the FNXNET51 module.
* Removed the DP memory for the MMU and replace it back with simple Registers, which means that when you reset the system, the MMU, Page0 will be reset back to the way it was. However, the caveat is that if you change between RAM to FLASH MMU default value, you need to do a reset, either a debug reset or General Reset because the MMU is now only 32bytes in Size, so, 4 pages of 8 values.
|-
| style="white-space:nowrap;"| F256Jr
| style="white-space:nowrap;"| Release Candidate 16
|?
| style="white-space:nowrap;" | 17-Nov-2023
| style="white-space:nowrap;"| [https://cdn.discordapp.com/attachments/1010352563406770217/1174998797991022632/F256M_WBh_Nov17th_2023_RC16_0111.jic F256M_WBh_Nov17th_2023_RC16_0111.jic]
|
* No Write Allowed when Debug Port writes in the MMU Memory Zone
* Incorporation of a new SPI Controller to interface with the FNXNET51 module using the NES/SNES MiniDin9 Connector
* ReSync of the Debug Generated RDY to stop the CPU. (untested)
|}

== FPGA Upgrade Guide ==

If you haven’t upgraded FPGAs before, below are some great videos to guide you.

You will need to download Quartus Prime Lite 18.1 Edition, since you are going to target a EP4CE15 FPGA (Cyclone 4).

Do not update to the latest version of Quartus Prime Lite, as the latest version doesn’t support that family of FPGA anymore and the software is very big.

Also, one might want to download only the "Intel® Quartus® Prime Programmer and Tools" as opposed to download the whole software by clicking on "Additional Software"

[https://www.intel.com/content/www/us/en/software-kit/665990/intel-quartus-prime-lite-edition-design-software-version-18-1-for-windows.html Intel Quartus Prime Lite Edition 18.1 for Windows]

[https://www.intel.com/content/www/us/en/software-kit/665988/intel-quartus-prime-lite-edition-design-software-version-18-1-for-linux.html Intel Quartus Prime Lite Edition 18.1 for Linux]

=== Video Guide ===

Note that the below Video Guide applies to both the F256K & F256Jr, despite it just being titled F256K.

==== How to Upgrade the F256K FPGA (and F256Jr) ====

<youtube>U7bq7t_qjxg</youtube>

=== Suggested USB Blaster ===

Earth People Technology
[https://www.amazon.ca/JTAG-Blaster-Intel-Altera-Programmer/dp/B07BZMSZ3G/ref=sr_1_3?crid=WWV8P0OHVCE3&keywords=altera+usb+blaster&qid=1688067039&sprefix=altera+usb+blaster%2Caps%2C113&sr=8-3]
[https://earthpeopletechnology.com/?wpsc-product=ept-2232h-sp-s1]

Terasic USB Blaster (low cost version)
[https://www.digikey.ca/en/products/detail/terasic-inc/P0302/2003484]
[https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=46#contents]

Chinese Knockoff (please avoid if possible)