Foenix F256 / Wildbits/K2 Wiki - User contributions [en]

WF16 Video Architecture

2026-04-15T01:12:09Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''F256'''
|1024
|888
|4×256
|0-3
|0-3
|No 4bpp, this is all 8bpp
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|666
|256×16
|—
|0-255
|Everything is sprites. RGB channels share low bit, 5551 = 16 bits
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

Scrolllable (requires stride or power-of-2 width/height etc) vs fixed (320x240|200 linear)

RLE vs uncompressed. If RLE is scrollable, it'll need the line index. If RLE is fixed, then spans can cross scanlines and it's basically a continuous 1d compression

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''F256'''
|—
|—
|—
| colspan="2" |Palette (0-3)
| colspan="3" |Tileset (0-7)
| colspan="8" |Tile (0-255)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64px tall (though 32px wide max) and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits? However, the initial scan of the sprite registers could assemble one linked list per layer. For each sprite, do vertical & horizontal clipping, if it's visible onscreen, then add it to the head of the linked list for its particular layer. 2 writes: update head pointer in layer, update next pointer in BRAM. This can be pipelined if needed. Then on render, multiple sprites can be set up simultaneously, if they don't overlap. So if we have 2 sprite renderer blocks, then if (xMax_Back ≥ xMin_Front) && (xMin_Back ≤ x2Front) then there is overlap and the back sprite stalls waiting for the front sprite to finish. Need to calculate the mask of pixels they need, which based on base pointer plus bit depth, yields a sparse list of addresses that need to be read. Now, I think all graphics need this computation and might be part of the actual ram bus driver to save space?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256'''
|2MB
|64
|8
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-04-15T00:04:53Z

WF: /* Bitmaps */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''F256'''
|1024
|888
|4×256
|0-3
|0-3
|No 4bpp, this is all 8bpp
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|666
|256×16
|—
|0-255
|Everything is sprites. RGB channels share low bit, 5551 = 16 bits
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

Scrolllable (requires stride or power-of-2 width/height etc) vs fixed (320x240|200 linear)

RLE vs uncompressed. If RLE is scrollable, it'll need the line index. If RLE is fixed, then spans can cross scanlines and it's basically a continuous 1d compression

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''F256'''
|—
|—
|—
| colspan="2" |Palette (0-3)
| colspan="3" |Tileset (0-7)
| colspan="8" |Tile (0-255)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits? However, the initial scan of the sprite registers could assemble one linked list per layer. For each sprite, do vertical & horizontal clipping, if it's visible onscreen, then add it to the head of the linked list for its particular layer. 2 writes: update head pointer in layer, update next pointer in BRAM. This can be pipelined if needed. Then on render, multiple sprites can be set up simultaneously, if they don't overlap. So if we have 2 sprite renderer blocks, then if (xMax_Back ≥ xMin_Front) && (xMin_Back ≤ x2Front) then there is overlap and the back sprite stalls waiting for the front sprite to finish. Need to calculate the mask of pixels they need, which based on base pointer plus bit depth, yields a sparse list of addresses that need to be read. Now, I think all graphics need this computation and might be part of the actual ram bus driver to save space?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256'''
|2MB
|64
|8
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-04-13T01:13:34Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''F256'''
|1024
|888
|4×256
|0-3
|0-3
|No 4bpp, this is all 8bpp
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|666
|256×16
|—
|0-255
|Everything is sprites. RGB channels share low bit, 5551 = 16 bits
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''F256'''
|—
|—
|—
| colspan="2" |Palette (0-3)
| colspan="3" |Tileset (0-7)
| colspan="8" |Tile (0-255)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits? However, the initial scan of the sprite registers could assemble one linked list per layer. For each sprite, do vertical & horizontal clipping, if it's visible onscreen, then add it to the head of the linked list for its particular layer. 2 writes: update head pointer in layer, update next pointer in BRAM. This can be pipelined if needed. Then on render, multiple sprites can be set up simultaneously, if they don't overlap. So if we have 2 sprite renderer blocks, then if (xMax_Back ≥ xMin_Front) && (xMin_Back ≤ x2Front) then there is overlap and the back sprite stalls waiting for the front sprite to finish. Need to calculate the mask of pixels they need, which based on base pointer plus bit depth, yields a sparse list of addresses that need to be read. Now, I think all graphics need this computation and might be part of the actual ram bus driver to save space?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256'''
|2MB
|64
|8
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

65816 C Compilers

2026-03-21T02:30:24Z

WF:

;[https://www.westerndesigncenter.com/wdc/tools.php WDC]
;[https://www.calypsi.cc/ Calypsi]
;[https://github.com/X65/K816 K816] (C-ish high level language)

WF16 Video Architecture

2026-03-13T17:02:52Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''F256'''
|1024
|888
|4×256
|0-3
|0-3
|No 4bpp, this is all 8bpp
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|666
|256×16
|—
|0-255
|Everything is sprites. RGB channels share low bit, 5551 = 16 bits
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''F256'''
|—
|—
|—
| colspan="2" |Palette (0-3)
| colspan="3" |Tileset (0-7)
| colspan="8" |Tile (0-255)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256'''
|2MB
|64
|8
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

IO Pages

2026-03-09T01:01:53Z

WF: /* $D000: Master Control Registers */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers 0-1 ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|MT_OVLY*
|MEMTEXT*
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

'''MEMTEXT''': Enable MEMTEXT mode (replaces text layer). Core2x only!

'''MT_OVLY''': Show BG in overlay mode when BG = 0. Core2x only!

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00A: Master Control Register 2 ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00A
|$F0:100A
|
|
|—
|—
|—
|—
|—
|—
|—
|Drawline Enable
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D180: Bresenham Lines (Core2x Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D180
|$F0:1180
|W
|
|—
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|
|
|R
|
|Busy
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|$D181
|$F0:1181
|
|
| colspan="8" |Color
|-
|$D182
|$F0:1182
|W
|
| colspan="8" |X0 (16 bit)
|-
|
|
|R
|
| colspan="8" |FIFO Data Count (13 bit, 8k depth)
|-
|$D184
|$F0:1184
|
|
| colspan="8" |X1 (16 bit)
|-
|$D186
|$F0:1186
|
|
| colspan="8" |Y0
|-
|$D187
|$F0:1187
|
|
| colspan="8" |Y1
|}
This shares timing with the 2nd bank of sprites, so the two are mutually exclusive.

BASIC Example:
1000 proc hwline(x0,y0,x1,y1,col)
1005 ?$D00A=1:?$D180=1:pokew $D182,0
1010 ?$D181=col:pokew $D182,x0:pokew $D184,x1
1020 ?$D186=y0:?$D187=y1
1030 ?$D180=3
1040 while (?$D180&$80)<>$80:wend
1045 ?$D00A=0
1050 endproc

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|''MASK0''*
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
<nowiki>*</nowiki> = Experimental in wf-dma cores, masks out $00 bytes from the source data, skipping writes for those pixels.

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

== IO Page 4 (Core2x Only) ==

=== $C000: LUT For MEMTEXT FG/BG Colors ===

== IO Page 4 (Core2x Only) ==

=== $C000: MEMTEXT Font Memory ===
4× Banks of 256 8×8 characters, or

2× Banks of 256 8×16 characters

IO Pages

2026-03-09T00:48:10Z

WF: /* $D180: Bresenham Lines */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D180: Bresenham Lines (Core2x Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D180
|$F0:1180
|W
|
|—
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|
|
|R
|
|Busy
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|$D181
|$F0:1181
|
|
| colspan="8" |Color
|-
|$D182
|$F0:1182
|W
|
| colspan="8" |X0 (16 bit)
|-
|
|
|R
|
| colspan="8" |FIFO Data Count (13 bit, 8k depth)
|-
|$D184
|$F0:1184
|
|
| colspan="8" |X1 (16 bit)
|-
|$D186
|$F0:1186
|
|
| colspan="8" |Y0
|-
|$D187
|$F0:1187
|
|
| colspan="8" |Y1
|}
This shares timing with the 2nd bank of sprites, so the two are mutually exclusive.

BASIC Example:
1000 proc hwline(x0,y0,x1,y1,col)
1005 ?$D00A=1:?$D180=1:pokew $D182,0
1010 ?$D181=col:pokew $D182,x0:pokew $D184,x1
1020 ?$D186=y0:?$D187=y1
1030 ?$D180=3
1040 while (?$D180&$80)<>$80:wend
1045 ?$D00A=0
1050 endproc

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|''MASK0''*
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
<nowiki>*</nowiki> = Experimental in wf-dma cores, masks out $00 bytes from the source data, skipping writes for those pixels.

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-03-09T00:36:40Z

WF: /* $D100: Bitmaps */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D180: Bresenham Lines =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D180
|$F0:1180
|W
|
|—
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|
|
|R
|
|Busy
|—
|—
|Reset
| colspan="2" |Bitmap #
|Start
|Enable
|-
|$D181
|$F0:1181
|
|
| colspan="8" |Color
|-
|$D182
|$F0:1182
|W
|
| colspan="8" |X0 (16 bit)
|-
|
|
|R
|
| colspan="8" |FIFO Data Count (13 bit, 8k depth)
|-
|$D184
|$F0:1184
|
|
| colspan="8" |X1 (16 bit)
|-
|$D186
|$F0:1186
|
|
| colspan="8" |Y0
|-
|$D187
|$F0:1187
|
|
| colspan="8" |Y1
|}
BASIC Example:
1000 proc hwline(x0,y0,x1,y1,col)
1005 ?$D00A=1:?$D180=1:pokew $D182,0
1010 ?$D181=col:pokew $D182,x0:pokew $D184,x1
1020 ?$D186=y0:?$D187=y1
1030 ?$D180=3
1040 while (?$D180&$80)<>$80:wend
1045 ?$D00A=0
1050 endproc

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|''MASK0''*
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
<nowiki>*</nowiki> = Experimental in wf-dma cores, masks out $00 bytes from the source data, skipping writes for those pixels.

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-03-09T00:18:27Z

WF: /* $DF00: DMA Controller */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|''MASK0''*
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
<nowiki>*</nowiki> = Experimental in wf-dma cores, masks out $00 bytes from the source data, skipping writes for those pixels.

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-03-08T21:17:49Z

WF: /* $DF00: DMA Controller */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|''MASK0''*
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
<nowiki>*</nowiki> = Experimental in wf-dma cores

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

FPU Accumulator

2026-03-08T06:31:08Z

WF:

This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.

There are 256 32-bit zeropage-like registers and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.

(TBD - registers in RAM or FPGA? Former allows swapping in new sets, but more complicated bus mastering, steal cpu cycles.)

Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.

Status bits (TBD) are available to read, with various errors, and integer as well as fp Z/N/V/C flags just like the 6502. V and C are only for integer ops.

* Overflow/underflow (fp/int range, as well as f2i)
* Division by zero
* Int conversion lost fractional portion

Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.

'''TODO''' - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness? Should all integer commands respect a single signedness control flag?

== Scripting ==
For optimization of applying a stream of mathematical ops in repetitive ways, you can save bytecodes in the FPGA registers. These are generally in the form of <code><op> <param></code> in terms of applying a write of byte <code>param</code> at op location <code><op></code>. This is fine for very fixed pipelines with input data always at one location. However, for general use this will require its own set of flow control and register indices to loop over sets of registers, indirect through computed register values, or receive "pointers" to a register and using offsets.

Op <code>run <reg></code> and <code>exit</code>, although these could nest generally to support subroutines. Not sure how to handle the stack.

Control flow would be unconditional loops, with tests to exit the loop on: Accumulator == 0, or offset = val.

=== Option 1: Offset register ===
Add another 8-bit "offset" register, and an enable bit to config. Op to write, set mask, or reset mask against the config register. When enabled, all registers have an offset added to it. Op to set the offset, or add a signed 8-bit value to the offset. This allows scripting to advance through the register set.

=== Option 2: Indirection ===
Have a mode bit for indirection. Any reg access will indirect through that register, but we'll need an offset for that as well? Annoying to swap between indirect and non-indirect, unless we move to 128 regs per bank?

'''TODO''' - directly support matrix multiplication and matrix addition, with width/height registers. Should hopefully be applicable to vector ops as well. BRAM is dual-ported, so we could read 2 registers to multiply per cycle, though multiplication is probably a couple of cycles. Could instantiate a couple of multipliers to really pipeline this hard.

The given register (offset ignored!) is input A, the "matrix param" is input B, register A + offset is the output register? But then we can't iterate matrices with the output register. But we also likely can't overwrite a matrix as we compute, because we're using it as an input. Don't want to waste LUT space copying a matrix into a reserved area. But we could also use regs 0-8 as a temp 3x3 matrix? Nah, that's another copying a matrix, dummy operation. This could be a 4-byte op instead of 2: MATMUL, A, B, Result? Have 3 registers, when you write to Result it triggers it? Writing a register should capture whether it's in RAM and the register bank number.
{| class="wikitable"
|+Config registers
!
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''Integer Control'''
|Signed
|64bit reg0
|—
| colspan="5" |Fixed point frac bits (0-31)
|-
|'''Mode'''
|RAM
|
|
|
| colspan="4" |Regnum Hi (0-1 for fpga)
|-
|'''Register offset'''
| colspan="8" |Offset
|-
|'''Matrix Size'''
| colspan="4" |Rows
| colspan="4" |Columns
|-
|'''Offset Enable'''
|All non-matrix
|—
|—
|—
|—
|Result
|MATB
|MATA
|-
|'''Bitmask'''
| colspan="8" |Mask, for setting/resetting
|-
|'''RAM Start'''
| colspan="8" |24-bit address? Or in multiples of 4kB banks?
|}
{| class="wikitable"
|+Shared Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|LOAD
|Reg
|A = Reg
|-
|
|STORE
|Reg
|Reg = A
|-
|
|SWAP
|Reg
|(A, Reg) = (Reg, A)
|-
|
|LEXTRA
|Ignored
|A = Extra
|-
|
|MASKW
|Reg
|Write mask to register
|-
|
|MASKS
|Reg
|Set mask bits in register
|-
|
|MASKC
|Reg
|Clear mask bits in register
|}
{| class="wikitable"
|+Floating Point Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|FADD
|Reg
|A = A + Reg
|-
|
|FSUB
|Reg
|A = A - Reg
|-
|
|FRSUB
|Reg
|A = Reg - A
|-
|
|FMUL
|Reg
|A = A * Reg
|-
|
|FDIV
|Reg
|A = A / Reg
|-
|
|FRDIV
|Reg
|A = Reg / A
|-
|
|F2I
|Signed flag
|A = Int(A) or UInt(A)
|-
|
|FMIN
|Reg
|A = Min(A, Reg)
|-
|
|FMAX
|Reg
|A = Max(A, Reg)
|-
|
|FABS
|Ignored
|A = Abs(A)
|-
| colspan="4" |Maybe
|-
|
|FADDB
|Byte
|A = A + Val
|-
|
|FSUBB
|Byte
|A = A - Val
|-
|
|FMULB
|Byte
|A = A * Val
|-
|
|FDIVB
|Byte
|A = A / Val
|-
|
|FCLR
|Ignored
|A = 0.0 (LOAD instead)
|-
|
|FNEG
|Ignored
|A = -A (FRSUB instead)
|-
|
|FRECIP
|Ignored
|A = 1.0/A (FRDIV instead)
|-
|
|FPOW
|Reg
|A = A ^ Reg
|-
|
|FSQRT
|Ignored
|A = Sqrt(A)
|-
|
|FTRIG
|0
|A = Sin(A)
|-
|
|
|1
|A = Cos(A)
|-
|
|
|2
|A = Tan(A)
|-
|
|FATAN
|Reg
|A = Atan(A, Reg)
|-
|
|
|
|A = Sec(A)
|-
|
|
|
|A = Csc(A)
|-
|
|
|
|A = Cot(A)
|-
|
|FACOT
|Reg
|A = Arccot(A, Reg)
|-
|
|
|
|A = Arcsin(A)
|-
|
|
|
|A = Arccos(A)
|-
|
|FFLOOR
|Reg
|A = Floor(A), Reg = Frac(A) (options?)
|-
|
|FCEIL
|Reg
|A = Ceil(A), Reg = Frac(A) (options?)
|}
{| class="wikitable"
|+Matrix Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|MATA
|Reg
|Set param A
|-
|
|MATB
|Reg
|Set param B
|-
|
|MATMUL
|Reg
|Reg = MATA * MATB
|-
|
|MATADD
|Reg
|Reg = MATA + MATB
|}
{| class="wikitable"
|+Integer Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|IADD
|Reg
|A = A + Reg
|-
|
|IADDC
|Reg
|A = A + Reg + C
|-
|
|ISUB
|Reg
|A = A - Reg
|-
|
|ISUBC
|Reg
|A = A - Reg - !C
|-
|
|IRSUB
|Reg
|A = Reg - A
|-
|
|ISETC
|0 or 1
|C = Value
|-
|
|IMUL
|Reg
|A = A * Reg (TBD - 64-bit result? Could auto-write Reg 0?)
|-
|
|IDIV
|Reg
|A = A / Reg (TBD - combined DIVMOD? 64/32 DIV?)
|-
|
|IMOD
|Reg
|A = A % Reg
|-
|
|ICMP
|Reg
|Status = A - Reg
|-
|
|INEG
|0
|A = -A
|-
|
|IAND
|Reg
|A = A & Reg
|-
|
|IOR
|Reg
|<nowiki>A = A | Reg</nowiki>
|-
|
|IXOR
|Reg
|A = A ^ Reg
|-
|
|I2F
|Signed Flag
|A = Float(Int(A)) or Float(UInt(A))
|-
|
|ISHL
|Count
|A = A << Value
|-
|
|ISHR
|Count
|A = A >> Value
|-
|
|ISSHR
|Count
|A = A >>(signed) Value
|-
|
|IROLL
|Count
|<nowiki>A = (A << Count) | (A >> (32 - Count))</nowiki>
|-
|
|IUMIN
|Reg
|A = Min(A, Reg)
|-
|
|ISMIN
|Reg
|A = Min(A, Reg)
|-
|
|IUMAX
|Reg
|A = Max(A, Reg)
|-
|
|ISMAX
|Reg
|A = Max(A, Reg)
|-
|
|IABS
|Ignored
|A = Abs(A)
|-
|
|ISET0
|Byte
|Set byte 0 of accumulator
|-
|
|ISET1
|Byte
|Set byte 1 of accumulator
|-
|
|ISET2
|Byte
|Set byte 2 of accumulator
|-
|
|ISET3
|Byte
|Set Byte 3 of accumulator
|}

WF FPGA Ideas

2026-03-03T00:25:07Z

WF: /* Memtext Bitmap */

== Video enhancements ==
[[WF16 Video Architecture]]

== Math coprocessor ==
[[FPU Accumulator]]

== SDCard ==
Auto-tx on read. Could supersede this with auto-reading a 16-bit length to a storage pointer, running in the background, flag or interrupt when done. Loading straight into DDR3 would be good once audio/video can read from there.

Stream MP3 or MIDI file from disk (or ddr3?) straight to chips

== Memtext Bitmap ==
Akin to the C64 hi-res bitmap mode, have a 640x480 1bpp bitmap with 8x8 color cells as defined by the existing memtext (or on-FPGA?) color attributes.

Font currently takes

Settings:

* Address of bitmap data (same as memtext font pointer)
* Choose cell-based (C64-like, follows 8x8 or 8x16 memtext selection) or linear pixel byte layout
* FPGA color matrix (2x 16-color) or RAM color matrix (2x 256-color)
It's annoying that this has its own separate palette, which takes up a lot of space, but I get it that it's a separate parallel pipeline to the "graphics" section. However, I'd rather just have it select which CLUT to use for FG and BG.

== Bootstrap and Machine Identity ==
Access to the cores SDCard. Name something better than the current hardcoded names.

Soft-boot into one of the other cores, instead of relying on jumpers to select the core. Have an extended PGZ header or new file format that can request such things. Note that PGZ should say how many and which 8k blocks or 64k banks it's hardcoded for. Should be another load format for "play nice" system tools that can be simultaneously loaded.

Identify cores by an 8 character ASCII string, instead of bit fields. Maybe have a version number (16 bit) per release of any named platform.

Have different ROM loads for different cores? Or boot from RAM if some magic bytes occur there instead of ROM., though that would be part of the ROM boot that can do that, what ISA would the code be?

RP2040 uses the Slave SelectMAX x8 config interface of the FPGA, and its 8 data pins should be GPIO for the FPGA to talk back to the RP after it's up and running (unless the pins are used for something else). The RP software needs updating for that.

Simplest comms would be splitting the 8-bit path into two 4-bit independent directional channels. Clock (toggle when new data is sent), Ack (receiver toggles when it's read), 2 data bits. All polled on the software end. The RP2040 could be crunching FAT32 stuff while the FPGA is waiting to write to it, no problem.

SRAM can be retained between resets:

<code>char my_crash_info[100] __attribute__((section(".uninitialized_data")));</code>

and with a macro:

<code>#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group</code>

<code>datetime_t __uninitialized_ram(persist_date);</code>

=== Tentatively Proposed RP2040 Startup ===

* Read SD Card for magic <code>/MYCORE.TXT</code> file containing the full path of the core filename to boot.
** If this exists, DIP switches can be some form of override. Need to be able to break in if something messes up. On configuring MYCORE, always tell the user to set their DIP switches to 00.
** If this doesn't exist, oldsk00l DIP switches determine the core to boot.
* Load compressed core file from card and get the FPGA going.
** Set the FPGA comm handshake pins to 0 before releasing the init/reset command to the FPGA.
* Load <code>/RPLIB</code> library and jump into it, if exists (else infinite loop). This runs whatever library functionality can talk to the FPGA, and is upgradable as a file through the loaded utilities.
The library should have functions to browse the cores sdcard, and select which file to boot with.

TODO - do the core selection DIP pins also hit the FPGA for flash banking? If so, then we might not be able to escape them.

== Timers ==
Ensure that the 24-bit value latches when the LSB is read (or the MSB is written?) for consistent reads.

== Wavetable Audio ==
Some form of wavetable audio is sorely missing for Amiga, TG16, SNES, Soundblaster era audio, especially sound effects. Basic multiple channels of stereo or panned mono, uncompressed samples, support some simple compression formats.

Pull small buffers of audio into the FPGA from RAM, keep 2 live at a time, one playing, one buffered. At 25MHz with a 48KHz sample rate, 1 sample lasts 520 cycles (20µsec), could be fast enough to fetch while the last sample is playing and just single-buffer it? Or even a rolling window Should also support just-in-time software generation of each buffer, with IRQ notifications.

Stretch samples to whatever the output sampling rate is. Linear interpolation would be neat, but probably optional. Same with the decay-to-zero that many old synth chips had.

== Sound Chip Instances ==
Instead of duplicating hardware instances of sound chips, multiplex all their registers and internal variables. Access would select 1 of them, and the hardware would run with that multiplexer active on all its values. Compare the size taken, depends on how complex the chip is.

Since sound chips don't need to be that fast, serially looping through and executing a cycle, accumulating their output, for the final audio sample would be fine. Some of them do this internally with their voices anyway.

Register to select which instance(s) to use, so programs can be agnostic to what sound context exists with other things. Probably expose 2 chips at a time through the IO registers, with a separate one to select which bank of 2 to use. At least for mono chips, or those which are commonly in pairs. Stereo chips could just have 1 register set exposed.

== 65816 support ==
Remap page 0 into any 64kB bank, allowing direct page, stack, etc, to have its own swappable space. However, need to consider how this goes for interrupts. An interrupt will probably have to remap to hardware bank 0, but then somehow restore the bank that used to be there. Keeping the upper 256 bytes locked somewhere (flash or bank 0 RAM) would solve that. The 8kB MMU can be used for these purposes already, but I wonder if the full bank swapping might be easier, but likely not really necessary as long as the MMU is around.

== FPGA-based CPU ==
65816 but with a genuine 16-bit data bus.

Keep 6809 in the same core with the 65816 running. Switch between either at any time (bus master), or alternate cycles. At core2x speed, they could each run at 6MHz alternately hitting the SRAM.

If the bus can be more dynamic, especially during vblank/hblank, the CPUs can run a lot faster there.

== Bitstream readers/writers ==
Write a byte or word to a FPGA location, it takes a CPU cycle to write it, and bumps its pointer.

For a bit stream, a 32-bit bitpointer covers 4Gb = 512MB. A write would need to know the width to write. Maybe 16 registers, write a value to one of those to declare how many bits from the written value to write. This actually allows the index register to determine width dynamically, which is nice. Both read & write interfaces should use this. A complete hack but easier to use would be to have 18 regs. For any width >8 bits, a 2nd access to the next register would grab the high byte, even though it's technically the trigger for the next higher. But this would get confusing in 65816 16-bit mode, accessing lower lengths.

Automatically converts between 32-bit bitstream pointer and 24-bit byte pointer + bit offset. When writing to the byte pointer, it automatically zeros out the bit offset, for easier initialization from standard word boundaries. If loading a bit pointer from normal pointer + bit offset, set the bit offset last.

Separate read & write context, so copies, decompression, etc, can be done. Bit pointers can be directly read/written as well. Direction is always in the positive direction, though, at least for now.

Probably good to support 0-length, for dynamically computed lengths. So with 0-16 supported, that's 17 entry points, kinda messy.

Also, skip forward N bits without a read or write. Technically this could just be a read N bits and ignore the value, but this should be 0-65535 bits skipped. Could also just do a 32-bit add on the pointer register.

8bit interface: 2 bitpointers, then 8 byte locs for pointer 0, and 8 byte locs for pointer 1.

16bit interface: 2 bitpointers, then 16 word locs for pointer 0, 16 word locs for pointer 1. Writes triggered on high byte write. Reads trigger on low byte read, which readies the high byte.

This is a CPU-blocking interface for reads, buffered for writes.

== Optical Keyboard ==
Can this be sent as 9 events of 8bits, instead of 8 events of 9 bits (2 bytes)? However the self-describing row number might be useful to keep.

== RLE Format(s) ==
RLE layers, DMA, and potentially sprites can use RLE encoding.
{| class="wikitable"
|+Span-based RLE formats
!bpp
!Layout
!length
!Max compression
!Breakeven
|-
|1
|<code>clllllll</code>
|1-128
|16:1 byte
|8px
|-
|2
|<code>cc111111</code>
|1-64
|16:1 byte
|4 pixels
|-
|4
|<code>ccccllll</code>
|1-16
|4:1 byte
|2 pixels
|-
|4
|<code>ccccCCCC llllllll llllllll</code>
|1-256
|170:1 byte (512:3)
|3+3 pixels
|-
|8
|<code>cccccccc llllllll</code>
|1-256
|128:1 byte
|2 pixels
|}
However, it would be useful to have spans of literal pixels as well, instead of just solid color span fills.

<code>0lllllll cccccccc</code> = span length L of color C, 0 = transparent

<code>1lllllll cccccccc...</code>= L count of individual pixels

For a bpp less than 8, probably require them to fill an even byte or word count

For now, RLE layers should be simple length + 8bpp aligned words. RLE bitmaps would be something different, maybe it's too flexible so we should just leave that to the CPU. It would save a lot of bandwidth for bitmap overlay layers with large transparent windows, though.

== DMA/Blitter ==
Maybe separate out 2d mode into its own blitter?

Flag to mask out the 'fill/mask' color (default 0)

Clip to output screen dimensions.

Xflip, yflip, maybe 90° rotation, but that means dest dimensions change? Scaling? Full affine transform?

Unpack RLE graphics, for better memory usage. Could still do x/y flip because this isn't raster-dependent. Must know the total x/y though if clipping is supported

Fields:

* bpp (could expand from src to dest given an offset?)
* src w/h/stride
* dest w/h/stride

'''TODO - V2'''

Clipping? Or should the src/dest be handled in software?

Ideally, there'd be a clip bounds defined at the dest address, w, h, stride, bpp. The source address is defined, and it's blitted into an x/y in the dest screen, automatically clipped. This could also be used as a pixel/stamp plotter.

If there end up being a large number of parameters for a src or dest, it would be nice to have multiple profiles. Either read src/dest profiles from ram, or have say 4 src & 4 dests saved, and blit from src N to dest M.

RLE graphics should probably save their w/h and mode implicitly as the first 2 words, as they are their own free-form shapes.

Since DMA currently only takes place during VBLANK, could be more efficient to have a DMA list to run when VSYNC hits, blasting those out as fast as possible.

For 1bpp (or maybe others, too?) and/or/nor/nand/xor modes would be necessary.

WF FPGA Ideas

2026-03-02T23:49:36Z

WF:

== Video enhancements ==
[[WF16 Video Architecture]]

== Math coprocessor ==
[[FPU Accumulator]]

== SDCard ==
Auto-tx on read. Could supersede this with auto-reading a 16-bit length to a storage pointer, running in the background, flag or interrupt when done. Loading straight into DDR3 would be good once audio/video can read from there.

Stream MP3 or MIDI file from disk (or ddr3?) straight to chips

== Memtext Bitmap ==
Akin to the C64 hi-res bitmap mode, have a 640x480 1bpp bitmap with 8x8 color cells as defined by the existing memtext (or on-FPGA?) color attributes.

Settings:

* Address of bitmap data (same as memtext font pointer)
* Choose cell-based (C64-like) or linear pixel byte layout
* FPGA color matrix (2x 16-color) or RAM color matrix (2x 256-color)

== Bootstrap and Machine Identity ==
Access to the cores SDCard. Name something better than the current hardcoded names.

Soft-boot into one of the other cores, instead of relying on jumpers to select the core. Have an extended PGZ header or new file format that can request such things. Note that PGZ should say how many and which 8k blocks or 64k banks it's hardcoded for. Should be another load format for "play nice" system tools that can be simultaneously loaded.

Identify cores by an 8 character ASCII string, instead of bit fields. Maybe have a version number (16 bit) per release of any named platform.

Have different ROM loads for different cores? Or boot from RAM if some magic bytes occur there instead of ROM., though that would be part of the ROM boot that can do that, what ISA would the code be?

RP2040 uses the Slave SelectMAX x8 config interface of the FPGA, and its 8 data pins should be GPIO for the FPGA to talk back to the RP after it's up and running (unless the pins are used for something else). The RP software needs updating for that.

Simplest comms would be splitting the 8-bit path into two 4-bit independent directional channels. Clock (toggle when new data is sent), Ack (receiver toggles when it's read), 2 data bits. All polled on the software end. The RP2040 could be crunching FAT32 stuff while the FPGA is waiting to write to it, no problem.

SRAM can be retained between resets:

<code>char my_crash_info[100] __attribute__((section(".uninitialized_data")));</code>

and with a macro:

<code>#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group</code>

<code>datetime_t __uninitialized_ram(persist_date);</code>

=== Tentatively Proposed RP2040 Startup ===

* Read SD Card for magic <code>/MYCORE.TXT</code> file containing the full path of the core filename to boot.
** If this exists, DIP switches can be some form of override. Need to be able to break in if something messes up. On configuring MYCORE, always tell the user to set their DIP switches to 00.
** If this doesn't exist, oldsk00l DIP switches determine the core to boot.
* Load compressed core file from card and get the FPGA going.
** Set the FPGA comm handshake pins to 0 before releasing the init/reset command to the FPGA.
* Load <code>/RPLIB</code> library and jump into it, if exists (else infinite loop). This runs whatever library functionality can talk to the FPGA, and is upgradable as a file through the loaded utilities.
The library should have functions to browse the cores sdcard, and select which file to boot with.

TODO - do the core selection DIP pins also hit the FPGA for flash banking? If so, then we might not be able to escape them.

== Timers ==
Ensure that the 24-bit value latches when the LSB is read (or the MSB is written?) for consistent reads.

== Wavetable Audio ==
Some form of wavetable audio is sorely missing for Amiga, TG16, SNES, Soundblaster era audio, especially sound effects. Basic multiple channels of stereo or panned mono, uncompressed samples, support some simple compression formats.

Pull small buffers of audio into the FPGA from RAM, keep 2 live at a time, one playing, one buffered. At 25MHz with a 48KHz sample rate, 1 sample lasts 520 cycles (20µsec), could be fast enough to fetch while the last sample is playing and just single-buffer it? Or even a rolling window Should also support just-in-time software generation of each buffer, with IRQ notifications.

Stretch samples to whatever the output sampling rate is. Linear interpolation would be neat, but probably optional. Same with the decay-to-zero that many old synth chips had.

== Sound Chip Instances ==
Instead of duplicating hardware instances of sound chips, multiplex all their registers and internal variables. Access would select 1 of them, and the hardware would run with that multiplexer active on all its values. Compare the size taken, depends on how complex the chip is.

Since sound chips don't need to be that fast, serially looping through and executing a cycle, accumulating their output, for the final audio sample would be fine. Some of them do this internally with their voices anyway.

Register to select which instance(s) to use, so programs can be agnostic to what sound context exists with other things. Probably expose 2 chips at a time through the IO registers, with a separate one to select which bank of 2 to use. At least for mono chips, or those which are commonly in pairs. Stereo chips could just have 1 register set exposed.

== 65816 support ==
Remap page 0 into any 64kB bank, allowing direct page, stack, etc, to have its own swappable space. However, need to consider how this goes for interrupts. An interrupt will probably have to remap to hardware bank 0, but then somehow restore the bank that used to be there. Keeping the upper 256 bytes locked somewhere (flash or bank 0 RAM) would solve that. The 8kB MMU can be used for these purposes already, but I wonder if the full bank swapping might be easier, but likely not really necessary as long as the MMU is around.

== FPGA-based CPU ==
65816 but with a genuine 16-bit data bus.

Keep 6809 in the same core with the 65816 running. Switch between either at any time (bus master), or alternate cycles. At core2x speed, they could each run at 6MHz alternately hitting the SRAM.

If the bus can be more dynamic, especially during vblank/hblank, the CPUs can run a lot faster there.

== Bitstream readers/writers ==
Write a byte or word to a FPGA location, it takes a CPU cycle to write it, and bumps its pointer.

For a bit stream, a 32-bit bitpointer covers 4Gb = 512MB. A write would need to know the width to write. Maybe 16 registers, write a value to one of those to declare how many bits from the written value to write. This actually allows the index register to determine width dynamically, which is nice. Both read & write interfaces should use this. A complete hack but easier to use would be to have 18 regs. For any width >8 bits, a 2nd access to the next register would grab the high byte, even though it's technically the trigger for the next higher. But this would get confusing in 65816 16-bit mode, accessing lower lengths.

Automatically converts between 32-bit bitstream pointer and 24-bit byte pointer + bit offset. When writing to the byte pointer, it automatically zeros out the bit offset, for easier initialization from standard word boundaries. If loading a bit pointer from normal pointer + bit offset, set the bit offset last.

Separate read & write context, so copies, decompression, etc, can be done. Bit pointers can be directly read/written as well. Direction is always in the positive direction, though, at least for now.

Probably good to support 0-length, for dynamically computed lengths. So with 0-16 supported, that's 17 entry points, kinda messy.

Also, skip forward N bits without a read or write. Technically this could just be a read N bits and ignore the value, but this should be 0-65535 bits skipped. Could also just do a 32-bit add on the pointer register.

8bit interface: 2 bitpointers, then 8 byte locs for pointer 0, and 8 byte locs for pointer 1.

16bit interface: 2 bitpointers, then 16 word locs for pointer 0, 16 word locs for pointer 1. Writes triggered on high byte write. Reads trigger on low byte read, which readies the high byte.

This is a CPU-blocking interface for reads, buffered for writes.

== Optical Keyboard ==
Can this be sent as 9 events of 8bits, instead of 8 events of 9 bits (2 bytes)? However the self-describing row number might be useful to keep.

== RLE Format(s) ==
RLE layers, DMA, and potentially sprites can use RLE encoding.
{| class="wikitable"
|+Span-based RLE formats
!bpp
!Layout
!length
!Max compression
!Breakeven
|-
|1
|<code>clllllll</code>
|1-128
|16:1 byte
|8px
|-
|2
|<code>cc111111</code>
|1-64
|16:1 byte
|4 pixels
|-
|4
|<code>ccccllll</code>
|1-16
|4:1 byte
|2 pixels
|-
|4
|<code>ccccCCCC llllllll llllllll</code>
|1-256
|170:1 byte (512:3)
|3+3 pixels
|-
|8
|<code>cccccccc llllllll</code>
|1-256
|128:1 byte
|2 pixels
|}
However, it would be useful to have spans of literal pixels as well, instead of just solid color span fills.

<code>0lllllll cccccccc</code> = span length L of color C, 0 = transparent

<code>1lllllll cccccccc...</code>= L count of individual pixels

For a bpp less than 8, probably require them to fill an even byte or word count

For now, RLE layers should be simple length + 8bpp aligned words. RLE bitmaps would be something different, maybe it's too flexible so we should just leave that to the CPU. It would save a lot of bandwidth for bitmap overlay layers with large transparent windows, though.

== DMA/Blitter ==
Maybe separate out 2d mode into its own blitter?

Flag to mask out the 'fill/mask' color (default 0)

Clip to output screen dimensions.

Xflip, yflip, maybe 90° rotation, but that means dest dimensions change? Scaling? Full affine transform?

Unpack RLE graphics, for better memory usage. Could still do x/y flip because this isn't raster-dependent. Must know the total x/y though if clipping is supported

Fields:

* bpp (could expand from src to dest given an offset?)
* src w/h/stride
* dest w/h/stride

'''TODO - V2'''

Clipping? Or should the src/dest be handled in software?

Ideally, there'd be a clip bounds defined at the dest address, w, h, stride, bpp. The source address is defined, and it's blitted into an x/y in the dest screen, automatically clipped. This could also be used as a pixel/stamp plotter.

If there end up being a large number of parameters for a src or dest, it would be nice to have multiple profiles. Either read src/dest profiles from ram, or have say 4 src & 4 dests saved, and blit from src N to dest M.

RLE graphics should probably save their w/h and mode implicitly as the first 2 words, as they are their own free-form shapes.

Since DMA currently only takes place during VBLANK, could be more efficient to have a DMA list to run when VSYNC hits, blasting those out as fast as possible.

For 1bpp (or maybe others, too?) and/or/nor/nand/xor modes would be necessary.

Getting Started

2026-02-27T02:19:45Z

WF: /* Powering your F256K and F256K2 */

== Getting Powered Up ==

=== Powering your F256K and F256K2 ===

The F256K is powered via a standard 2.5mm DC Connector, which takes a centre-positive 12V 2A capable Power Supply.

It's possible to use 9 V instead of 12 V, (''I can personally vouch for it -Mu0n''). Typical power draw is a little under 4 W.

This type of power supply is quite common. [https://www.amazon.com/Adapter-100-240V-Transformer-Charger-Security/dp/B091XSVV1Y Example 12V 2A capable power supply] (used by at least 1 Discord user successfully)

The F256K2's higher end FPGA requires adding a [https://www.amazon.com/dp/B08CMK8BMT compatible heatsink] if you're running advanced cores like the upcoming 68k core, but is not required for the default K2c/e, 6809, or Core2x.

=== Powering your F256Jr and (?) F256Jr.Jr ===

The F256Jr is supplied as a Mini-ITX form factor mainboard, with a standard 24 pin ATX power supply connector for power connectivity.

Since the F256Jr needs relatively little power, compared to a mini-ATX PC, a popular DC 12V 24pin Pico ATX PSU works well and is a compact solution.

* [https://www.amazon.com/dp/B08F57GKCL Pico PSU] - You power the Pico PSU via a 12V DC center-positive Power Supply source.
* [https://www.amazon.com/dp/B07MXXXBV8 12V DC center-positive A/C Adapter] - Commonly used to power the Pico PSU.
The board itself has no power switch. If you do not have a Mini-ITX case, a pin header on the board can be bridged by a jumper and thereby used instead of a proper power switch as a stop gap solution. In this picture https://wiki.c256foenix.com/images/6/64/Pinout_Jr_December_7th_Trans.png the pin header in question is shown in the lower right and is labeled with ''PW ON SPST Switch''.

== Getting programs onto the F256 ==

=== SD Card ===

The F256K, F256K2, F256JR and F256Jr.Jr. have an SD card slot. The device software to read the SD card is a bit touchy (it's inherited from the Commander X16 project) and doesn't work with all SD cards

* Cards should support the V2 protocol (HC or XC); older cards that only support the V1 protocol (typically 2GB or less) won't work. By contrast, the kernels for the C256 machines generally only work with V1 cards. Note that, in both cases, this is a software limitation -- all of the Foenix machines are electrically capable of using both kinds of cards.
* Partitioning should be MBR, and partition type 0x0c.
* Cards *MUST* be formatted FAT32 -- **NOT: FAT, FAT12, FAT16, or exFAT**.
* Formatting with Windows 10/11 works fine, but make sure to force FAT32 (or use the command line: <code>format /FS:FAT32 H:</code>)
* Formatting with MacOS will only work using the <code>diskutil</code> command line utility. An example usage looks like this: <code>sudo diskutil eraseDisk FAT32 [DiskName] MBRFormat /dev/[DiskNumber]</code>. You can use <code>diskutil list</code> to get the disk number for the SD Card.
* Formatting and partitioning SD cards with Linux can be done using the <code>gnome-disk-utility</code> (known simply as Disks) and is installed on most mainstream distributions of Linux. Disks will access all the drives on the computer so be sure you have the SD card selected when editing. [https://wiki.gnome.org/Apps/Disks Gnome/Disks wiki]
* FAT32 only supports a maximum partition size of 32Gb, on larger cards you will need to create multiple partitions -- however, only the first is recognized by DOS.
* Some folks have had luck formatting cards with the [https://www.sdcard.org/downloads/formatter/sd-memory-card-formatter-for-windows-download/ Official SD Association formatter for Windows].

=== Curated Software Collections ===

* [https://github.com/Mu0n/F256MiscGoodies/tree/main/SDCard_Collection Go here to get a nice curated collection of programs] - it was first pepared for VCF East 2025 for the showroom Foenix table, but it is actively getting further updates. simply unzip it to the root of the flash card. You are encouraged to browse and launch most things with the f/manager program by first diving into /- fm from superbasic.
* An older 2023 pack can be found here (and is referenced down below in the SuperBasic section of this current page), simply unzip it to the root of the flash card: [https://github.com/FoenixRetro/Documentation/blob/main/f256/archive older demo pack from 2023]

=== Tutorial Video on 13 methods on running programs: ===
<youtube>0ShFv89KGDs</youtube>

00:41 Method 1 - SuperBasic program

01:51 Method 2 - .pgz, .pgZ or .pgx executable from SuperBasic

03:12 Method 3 - Program residing in flash memory

05:58 Method 4 - .pgz, .pgZ or .pgx from DOS

07:31 Method 5 - f/manager utility

12:31 Method 6 - 5.25" 1541 Commodore Disk Drive

14:08 Method 7 - FoenixMgr python scripts for .pgz, .pgZ or .pgx

17:52 Method 8 - FoenixMgr python scripts for .bin

22:21 Method 9 - FoenixMgr modifying the flash programs

25:41 Method 10 - Fcart & PGZ2FLASH to program a Flash Cartridge

28:58 Method 10b - PGZ2Flash to program a Flash Program

30:01 Method 11 - Fcart to REPROGRAM a Flash Cartridge

33:51 Method 12 - Toolbox environment in 65816 extended mode

=== Debug USB port ===

* This is what most developers use as it's the most convenient. Connect the debug USB port to your PC or Mac

* You can use:
** [https://github.com/pweingar/FoenixMgr FoenixMgr] - works on Windows, Mac, Linux
*** A Python script to manage the Foenix series of retro style computers through their USB debug ports. This tool allows uploading files of various formats to system RAM, and displaying memory through various means.

** [https://github.com/Trinity-11/FoenixIDE FoenixIDE] (Windows only)
*** Development and Debugging Suite for the C256 Foenix Family of Computers.

=== wget ===
If you have the [[wifi]] configured, you can use [https://github.com/ghackwrench/F256_wget wget] to pull programs and data right off the web!

== SuperBASIC ==

The machine boots to SuperBASIC. SuperBASIC is inspired by BBC BASIC but offers quite a bit more.

* Read the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual].

* Watch EMWhite's excellent intro series on Youtube:
** Full Playlist here: [https://www.youtube.com/playlist?list=PLeHjTvk7NPiSqGz4REMH-S4hjYpLS2YNR EMWhite's Intro Series - Full Playlist].
** Part 1 can be viewed here:
<youtube>G_S2c_MsqYA</youtube>

To get started, you can type in a sample program at the command prompt:

<pre>
10 for i=1 to 5
20 print "Hello world"
30 next
run
</pre>

SuperBASIC is similar to CBM (Microsoft) BASIC but has some differences. For example, note in the sample above it's just <code>next</code> not <code>next i</code>.

The first 15 or so pages of the [https://github.com/FoenixRetro/f256-superbasic/blob/main/reference/source/f256jr_basic_ref.pdf SuperBASIC Reference Manual] are quite instructive.

SuperBASIC is actually much more powerful and supports structured programming (procedures, blocks etc.)

<code>dir</code> - Run this to display directory of SD card

Loading & running programs off of the SD card is similarly easy:

<pre>
load "JrWordl.bas"
run
</pre>

Similar to the C64, you can save time in loading programs from the <code>dir</code> listing by using your cursor keys to go up to the entry, typing <code>load "</code> (insert mode is active by default) etc. You can use <code>CTRL+E</code> to jump to the end of the line and use <code>CTRL+K</code> to delete any text from the cursor to the end of the line. Correctly place the closing <code>"</code> and hit <code>ENTER</code>.

<code>CTRL+C</code> acts as a "break" command and stops any running SuperBASIC program or <code>LIST</code> command.

Read built-in help/reference:

<code>/help</code> : But '''NOTE''', this erases BASIC memory! Use Backspace key to go back in menus and to exit.

Explore the included demo SuperBASIC programs:

{| class="wikitable"
! Program !! Notes !! Source
|-
| <code>JrWordl.bas</code> || Wordle game, guess 5 letter word ||
|-
| <code>mandel.bas</code> || Draws Mandlebrot set in graphics mode, takes between 2 and 3 hours || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>rpg-demo.bas</code> || UI sample that shows Zelda like RPG game. Control the character with an Atari-joystick connected to JoyPort1 || @econtrerasd
|-
| <code>Problematic_Code.bas</code> || Displays scrolling starfield ||
|-
| <code>noelrl.bas</code> || Simple integer BASIC bench mark from Noel's retro lab. Completes < 3.5 seconds, compares very favourably to other retro systems! || [https://www.youtube.com/watch?v=H05hM_Guoqk Youtube]
|-
| <code>dance.bas</code> || Animates sprite of dancer || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>luna.bas</code> || Displays simple scene ||
|-
| <code>blink.bas</code> || Blinks drive access light || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|-
| <code>piano.bas</code> || Play some notes with the PSG || [https://github.com/Mu0n/F256KbasicBASICdoodles @Mu0n]
|}

=== Running pgz, pgZ, pgx Executable Files ===
Running executables from superbasic involves calling the "pexec program" normally stored in Flash memory, but which is written as simply as possible with a "-" (dash symbol without the quotes) to make it easy and convenient to run programs.

You can use this notation to execute file.pgz (the same can be done with pgx, pgZ):<pre>
/- file.pgz
</pre>The / is for running anything that's stored in flash

The - is the special alias for pexec, as it is stored in flash

Therefore /- is used together to launch an executable, which would follow as the first argument to the right. Keep in mind you need a space between /- and your program name.

=== More Resources ===
=== This Wiki ===

Explore all of the content of this Wiki, to expand your F256 series knowledge!

=== Discord ===

The [https://discord.gg/9vjUEGgcUS Foenix Retro Systems Discord] is the primary place to get questions answered.

Also, if you resolve your question, and you didn't find the answer here on the Wiki, '''''please consider contributing to the Wiki''''', for the benefit of others with the same question!

=== Foenix Retro Systems Newsletter ===

Read back issues [http://apps.emwhite.org/foenixmarketplace/ here] (also a great source for sample programs).

Issues starting at #4 cover the F256 line. Issues 1-3 cover the previous version of the hardware (C256), although there are still many salient points.

=== Youtube Channels with regular Foenix videos ===
Official Foenix Retro Systems channel: https://www.youtube.com/@foenixretrosys

8-Bit Wall of Doom (from EMWhite): https://www.youtube.com/@8-bitwallofdoom

AnyBit Fever Dreams (from Mu0n): https://www.youtube.com/@anybitfeverdreams

Boisy Pitre (from MrPitre): https://www.youtube.com/@boisypitre

digarok (from digarok): https://www.youtube.com/@digarok

Micah Bly (from Micah): https://www.youtube.com/@micahbly8241

NormanYen (from beethead): https://www.youtube.com/@normanyen5720

Programmer vs World (from PlasmaTrout): https://makertube.net/c/programmervsworld/videos

==== Specific youtube videos from heavy hitters: ====
Jan Beta reviews the F256K: https://www.youtube.com/watch?v=57FuA8YuXn0

Perifractic (from Retro Recipes) reviews the F256K: https://www.youtube.com/watch?v=TJQgecozNzU

IO Pages

2026-02-25T23:52:28Z

WF: /* $D018: Raster */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T23:51:40Z

WF: /* $D018: Raster */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T23:49:12Z

WF: /* $D018: Raster */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles from SOF)
|-
|43
|$02B
|DMA safety zone, disabled from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T23:47:59Z

WF: /* $D018: Raster */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and non-Core2xDMA
|-
|2
|$002
|Core2x: DMA starts halfway through here (8192 SRAM cycles from SOF)
|-
|43
|$02B
|DMA safety zone, disabled from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T23:19:48Z

WF: /* $D018: Raster */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and DMA
|-
|43
|$02B
|DMA safety zone, disabled from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

User:WF

2026-02-25T22:56:57Z

WF:

Scratchpad for working on Foenijs. Feature requests are welcome

[[WF FPGA Ideas]]

[[Foenijs]]

[[SuperBASIC Wiki Reference]]

== Debugger Features ==
+ = implemented, - = unimplemented

=== Stepping ===
+ Step 1 cycle

- Step N cycles (easy, just not exposed now)

+ Step to next raster line

+ Step to next frame

+ Step to IRQ

+ Step to RTI

+ Step Out (run until stack shrinks from the starting point)

=== Breakpoints ===
+ Break on 16-bit PC (raw CPU PC) <code>machine.cpu.breakpoints16[]</code>

+ Break on 24-bit PC (post-MMU resolved address) <code>machine.cpu.breakpoints24[]</code>

- Break on 24-bit address read <code>machine.mmu.breakOnRead[]</code>

+ Break on 24-bit address write (I/O only for now) <code>machine.mmu.breakOnWrite[]</code>

+ Break on BRK <code>machine.cpu.breakOptions.breakOnBRK</code>

+ Break on IRQ/NMI <code>machine.cpu.breakOptions.breakOnIRQ</code> <code>.breakOnNMI</code>

+ Break on undocumented NOP (eg unexpected bytes) <code>machine.cpu.breakOptions.breakOnBadNOP</code>

+ Break on RTI <code>machine.cpu.breakOptions.breakOnRTI</code>

+ Break on single-instruction infinite loop <code>machine.cpu.breakOptions.breakOnInfiniteLoop</code>

=== Printing/Logging/Viewing ===
+ Log IRQ <code>machine.cpu.breakOptions.logIRQ</code>

+ Log BRK (always on for now)

- Log SOF

+ Capture CPU execution log, <code>machine.cpu.debug</code> to enable, <code>machine.cpu.log(n)</code> to print, n is optional number of instructions

+ Live updated memory view (lame, scroll through full memory)

- Create any number of live memory views of different sizes & locations

+ Stack entry provenance tracking

- Upload labels file

IO Pages

2026-02-25T22:05:39Z

WF: /* $D650: Interval Timers */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T21:56:23Z

WF: /* $D650: Interval Timers */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T21:50:52Z

WF: /* $DF00: DMA Controller */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes!
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-25T21:26:07Z

WF: /* $D650: Timers */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Interval Timers ======
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes!
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-23T15:18:20Z

WF: /* $D900: Sprites */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-23T02:19:43Z

WF: /* $D200: Tilemaps */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

IO Pages

2026-02-23T02:18:44Z

WF: /* $D200: Tilemaps */ better scroll description

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
|—
| colspan="3" |8x8 SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|—
| colspan="3" |8x8 SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
'''**''' = For 8×8px tilesets, the first map entry (2 bytes) seems to be skipped, so the pointer needs to point 2 bytes before the actual upper-left starting entry.

For 16×16px tilesets, the tile map pointer directly points to the first entry. Very old cores might have had the same offset required.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

Memory Management

2026-02-22T04:56:28Z

WF: /* Numerical address computations for SRAM/VICKY pointers */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FFFF
|64k
|Core2x: 8×8kB MMU banked
F256K2e: SRAM, except last 256 bytes
|-
|$00:FF00 - $00:FFFF
|256
|F256K2e only: Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. Devices are laid out every 64 ($40) blocks (512kB).

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="10" |Block Number
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block offset in device (00-3F)
|-
| colspan="25" |
|-
|'''16-bit MMU Address'''
| colspan="8" |
| colspan="3" |MLUT Number
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM (0), Flash (1), Cartridge (2), or Reserved (3)

===== Numerical address computations for SRAM/VICKY pointers =====
Full Gen 2 2MB:

<code>SRAM address = ((MMU Block & 0x300) << 11) | ((MMU Block & 0x03F) << 13) | (Byte offset)</code>

<code>MMU Block number = ((SRAM Address & 0x180000) >> 11) | ((SRAM address & 0x07e000) >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

Gen 1, or only using the first 512kB:

<code>SRAM address = (MMU Block << 13) | (Byte offset)</code>

<code>MMU Block number = (SRAM address >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Flat/SRAM Address

! scope=col | Block Number
! scope=col | Flat/SRAM Address

! scope=col | Block Number
! scope=col | Flat/SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-22T03:58:45Z

WF: /* Memory Block Tables */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FFFF
|64k
|Core2x: 8×8kB MMU banked
F256K2e: SRAM, except last 256 bytes
|-
|$00:FF00 - $00:FFFF
|256
|F256K2e only: Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. Devices are laid out every 64 ($40) blocks (512kB).

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="10" |Block Number
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block offset in device (00-3F)
|-
| colspan="25" |
|-
|'''16-bit MMU Address'''
| colspan="8" |
| colspan="3" |MLUT Number
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM (0), Flash (1), Cartridge (2), or Reserved (3)

===== Numerical address computations for SRAM/VICKY pointers =====
Full Gen 2 2MB:

<code>SRAM address = ((MMU Block & 0x300) << 11) | ((MMU Block & 0x03F) << 13) | (Byte offset)</code>

<code>MMU Block number = ((SRAM Address & 0x180000) >> 11) | ((SRAM address & 0x07fe000) >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

Gen 1, or only using the first 512kB:

<code>SRAM address = (MMU Block << 13) | (Byte offset)</code>

<code>MMU Block number = (SRAM address >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Flat/SRAM Address

! scope=col | Block Number
! scope=col | Flat/SRAM Address

! scope=col | Block Number
! scope=col | Flat/SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-22T03:57:48Z

WF: /* 8kB Block Layout */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FFFF
|64k
|Core2x: 8×8kB MMU banked
F256K2e: SRAM, except last 256 bytes
|-
|$00:FF00 - $00:FFFF
|256
|F256K2e only: Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. Devices are laid out every 64 ($40) blocks (512kB).

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="10" |Block Number
|-
|'''MLUT Entry'''
| colspan="14" |
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block offset in device (00-3F)
|-
| colspan="25" |
|-
|'''16-bit MMU Address'''
| colspan="8" |
| colspan="3" |MLUT Number
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM (0), Flash (1), Cartridge (2), or Reserved (3)

===== Numerical address computations for SRAM/VICKY pointers =====
Full Gen 2 2MB:

<code>SRAM address = ((MMU Block & 0x300) << 11) | ((MMU Block & 0x03F) << 13) | (Byte offset)</code>

<code>MMU Block number = ((SRAM Address & 0x180000) >> 11) | ((SRAM address & 0x07fe000) >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

Gen 1, or only using the first 512kB:

<code>SRAM address = (MMU Block << 13) | (Byte offset)</code>

<code>MMU Block number = (SRAM address >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T20:27:24Z

WF: /* Flat Memory Models */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FFFF
|64k
|Core2x: 8×8kB MMU banked
F256K2e: SRAM, except last 256 bytes
|-
|$00:FF00 - $00:FFFF
|256
|F256K2e only: Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion. Devices are laid out every 64 ($40) blocks (512kB).

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''MLUT'''
| colspan="14" |
| colspan="10" |Block Number
|-
|'''MLUT'''
| colspan="14" |
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block offset in device (00-3F)
|-
| colspan="25" |
|-
|'''16-bit MMU Address'''
| colspan="8" |
| colspan="3" |MLUT Entry
| colspan="13" |Byte offset in 8k block
|-
|'''16-bit MMU Address'''
| colspan="8" |
| colspan="3" |MLUT Entry
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block offset in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM (0), Flash (1), Cartridge (2), or Reserved (3)

===== Numerical address computations for SRAM/VICKY pointers =====
Full Gen 2 2MB:

<code>SRAM address = ((MMU Block & 0x300) << 11) | ((MMU Block & 0x03F) << 13) | (Byte offset)</code>

<code>MMU Block number = ((SRAM Address & 0x180000) >> 11) | ((SRAM address & 0x07fe000) >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

Gen 1, or only using the first 512kB:

<code>SRAM address = (MMU Block << 13) | (Byte offset)</code>

<code>MMU Block number = (SRAM address >> 13)</code>

<code>MMU byte offset = SRAM Address & 0x001fff</code>

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T19:59:37Z

WF: /* Flat Memory Models */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FFFF
|64k
|Core2x: 8×8kB MMU banked
F256K2e: SRAM, expect last 256 bytes
|-
|$00:FF00 - $00:FFFF
|256
|F256K2e only: Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''Block'''
|—
| colspan="10" |MMU Block Number
| colspan="13" |Byte offset in 8k block
|-
|'''Block'''
|—
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T19:41:03Z

WF: /* Memory Block Tables */

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FEFF
|64k - 256
|Core2x: 8×8kB MMU banked
F256K2e: SRAM
|-
|$00:FF00 - $00:FFFF
|256
|Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''Block'''
|—
| colspan="10" |MMU Block Number
| colspan="13" |Byte offset in 8k block
|-
|'''Block'''
|—
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat/SRAM Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address

! scope=col | Block Number
! scope=col | SRAM Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T18:06:07Z

WF: /* 8kB Block Layout */ fixed block to flat construction table

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FEFF
|64k - 256
|Core2x: 8×8kB MMU banked
F256K2e: SRAM
|-
|$00:FF00 - $00:FFFF
|256
|Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+MMU Block Address Construction
!
!23
!22
!21
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''Block'''
|—
| colspan="10" |MMU Block Number
| colspan="13" |Byte offset in 8k block
|-
|'''Block'''
|—
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
| colspan="25" |
|-
|'''Flat SRAM'''
|0
|0
|0
| colspan="2" |''Expansion''
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Flash'''
|1
|1
|1
|1
|1
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|-
|'''Flat Cart'''
|1
|1
|1
|1
|0
| colspan="6" |Block number in device (00-3F)
| colspan="13" |Byte offset in 8k block
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T17:43:23Z

WF: /* 8kB Block Layout */ Fixed block to flat mapping

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FEFF
|64k - 256
|Core2x: 8×8kB MMU banked
F256K2e: SRAM
|-
|$00:FF00 - $00:FFFF
|256
|Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
!Flat address
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|$00:0000 - $07:FFFF
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|$F8:0000 - $FF:FFFF
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|$F4:0000 - $F7:FFFF
|-
|$A0 - $FF||Reserved
|
|
|-
! colspan="3" |''Core2x expansion''
!
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|$08:0000 - $0F:FFFF
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|$10:0000 - $17:FFFF
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|$18:0000 - $1F:FFFF
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|
|}

{| class="wikitable"
|+Final MMU Address Construction
!''22''
!''21''
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
| colspan="10" |MMU Block Number
| colspan="13" rowspan="2" |Byte offset in 8k block
|-
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same flash addresses, and $80, $180, $280, $380 all point to the same expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T17:39:16Z

WF: /* Memory Block Tables */ Fixing memory block tables

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FEFF
|64k - 256
|Core2x: 8×8kB MMU banked
F256K2e: SRAM
|-
|$00:FF00 - $00:FFFF
|256
|Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|-
|$A0 - $FF||Reserved
|
|-
! colspan="3" |''Core2x expansion''
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|}

{| class="wikitable"
|+Final MMU Address Construction
!''22''
!''21''
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
| colspan="10" |MMU Block Number
| colspan="13" rowspan="2" |Byte offset in 8k block
|-
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same physical flash, and $80, $180, $280, $380 all point to the same physical expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address

! scope=col | Block Number
! scope=col | Flat Address
|-
|$100||$08:0000 - $08:1FFF||$200||$10:0000 - $10:1FFF||$300||$18:0000 - $18:1FFF
|-
|$101||$08:2000 - $08:3FFF||$201||$10:2000 - $10:3FFF||$301||$18:2000 - $18:3FFF
|-
|$102||$08:4000 - $08:5FFF||$202||$10:4000 - $10:5FFF||$302||$18:4000 - $18:5FFF
|-
|$103||$08:6000 - $08:7FFF||$203||$10:6000 - $10:7FFF||$303||$18:6000 - $18:7FFF
|-
|$104||$08:8000 - $08:9FFF||$204||$10:8000 - $10:9FFF||$304||$18:8000 - $18:9FFF
|-
|$105||$08:A000 - $08:BFFF||$205||$10:A000 - $10:BFFF||$305||$18:A000 - $18:BFFF
|-
|$106||$08:C000 - $08:DFFF||$206||$10:C000 - $10:DFFF||$306||$18:C000 - $18:DFFF
|-
|$107||$08:E000 - $08:FFFF||$207||$10:E000 - $10:FFFF||$307||$18:E000 - $18:FFFF
|-
|$108||$09:0000 - $09:1FFF||$208||$11:0000 - $11:1FFF||$308||$19:0000 - $19:1FFF
|-
|$109||$09:2000 - $09:3FFF||$209||$11:2000 - $11:3FFF||$309||$19:2000 - $19:3FFF
|-
|$10A||$09:4000 - $09:5FFF||$20A||$11:4000 - $11:5FFF||$30A||$19:4000 - $19:5FFF
|-
|$10B||$09:6000 - $09:7FFF||$20B||$11:6000 - $11:7FFF||$30B||$19:6000 - $19:7FFF
|-
|$10C||$09:8000 - $09:9FFF||$20C||$11:8000 - $11:9FFF||$30C||$19:8000 - $19:9FFF
|-
|$10D||$09:A000 - $09:BFFF||$20D||$11:A000 - $11:BFFF||$30D||$19:A000 - $19:BFFF
|-
|$10E||$09:C000 - $09:DFFF||$20E||$11:C000 - $11:DFFF||$30E||$19:C000 - $19:DFFF
|-
|$10F||$09:E000 - $09:FFFF||$20F||$11:E000 - $11:FFFF||$30F||$19:E000 - $19:FFFF
|-
|$110||$0A:0000 - $0A:1FFF||$210||$12:0000 - $12:1FFF||$310||$1A:0000 - $1A:1FFF
|-
|$111||$0A:2000 - $0A:3FFF||$211||$12:2000 - $12:3FFF||$311||$1A:2000 - $1A:3FFF
|-
|$112||$0A:4000 - $0A:5FFF||$212||$12:4000 - $12:5FFF||$312||$1A:4000 - $1A:5FFF
|-
|$113||$0A:6000 - $0A:7FFF||$213||$12:6000 - $12:7FFF||$313||$1A:6000 - $1A:7FFF
|-
|$114||$0A:8000 - $0A:9FFF||$214||$12:8000 - $12:9FFF||$314||$1A:8000 - $1A:9FFF
|-
|$115||$0A:A000 - $0A:BFFF||$215||$12:A000 - $12:BFFF||$315||$1A:A000 - $1A:BFFF
|-
|$116||$0A:C000 - $0A:DFFF||$216||$12:C000 - $12:DFFF||$316||$1A:C000 - $1A:DFFF
|-
|$117||$0A:E000 - $0A:FFFF||$217||$12:E000 - $12:FFFF||$317||$1A:E000 - $1A:FFFF
|-
|$118||$0B:0000 - $0B:1FFF||$218||$13:0000 - $13:1FFF||$318||$1B:0000 - $1B:1FFF
|-
|$119||$0B:2000 - $0B:3FFF||$219||$13:2000 - $13:3FFF||$319||$1B:2000 - $1B:3FFF
|-
|$11A||$0B:4000 - $0B:5FFF||$21A||$13:4000 - $13:5FFF||$31A||$1B:4000 - $1B:5FFF
|-
|$11B||$0B:6000 - $0B:7FFF||$21B||$13:6000 - $13:7FFF||$31B||$1B:6000 - $1B:7FFF
|-
|$11C||$0B:8000 - $0B:9FFF||$21C||$13:8000 - $13:9FFF||$31C||$1B:8000 - $1B:9FFF
|-
|$11D||$0B:A000 - $0B:BFFF||$21D||$13:A000 - $13:BFFF||$31D||$1B:A000 - $1B:BFFF
|-
|$11E||$0B:C000 - $0B:DFFF||$21E||$13:C000 - $13:DFFF||$31E||$1B:C000 - $1B:DFFF
|-
|$11F||$0B:E000 - $0B:FFFF||$21F||$13:E000 - $13:FFFF||$31F||$1B:E000 - $1B:FFFF
|-
|$120||$0C:0000 - $0C:1FFF||$220||$14:0000 - $14:1FFF||$320||$1C:0000 - $1C:1FFF
|-
|$121||$0C:2000 - $0C:3FFF||$221||$14:2000 - $14:3FFF||$321||$1C:2000 - $1C:3FFF
|-
|$122||$0C:4000 - $0C:5FFF||$222||$14:4000 - $14:5FFF||$322||$1C:4000 - $1C:5FFF
|-
|$123||$0C:6000 - $0C:7FFF||$223||$14:6000 - $14:7FFF||$323||$1C:6000 - $1C:7FFF
|-
|$124||$0C:8000 - $0C:9FFF||$224||$14:8000 - $14:9FFF||$324||$1C:8000 - $1C:9FFF
|-
|$125||$0C:A000 - $0C:BFFF||$225||$14:A000 - $14:BFFF||$325||$1C:A000 - $1C:BFFF
|-
|$126||$0C:C000 - $0C:DFFF||$226||$14:C000 - $14:DFFF||$326||$1C:C000 - $1C:DFFF
|-
|$127||$0C:E000 - $0C:FFFF||$227||$14:E000 - $14:FFFF||$327||$1C:E000 - $1C:FFFF
|-
|$128||$0D:0000 - $0D:1FFF||$228||$15:0000 - $15:1FFF||$328||$1D:0000 - $1D:1FFF
|-
|$129||$0D:2000 - $0D:3FFF||$229||$15:2000 - $15:3FFF||$329||$1D:2000 - $1D:3FFF
|-
|$12A||$0D:4000 - $0D:5FFF||$22A||$15:4000 - $15:5FFF||$32A||$1D:4000 - $1D:5FFF
|-
|$12B||$0D:6000 - $0D:7FFF||$22B||$15:6000 - $15:7FFF||$32B||$1D:6000 - $1D:7FFF
|-
|$12C||$0D:8000 - $0D:9FFF||$22C||$15:8000 - $15:9FFF||$32C||$1D:8000 - $1D:9FFF
|-
|$12D||$0D:A000 - $0D:BFFF||$22D||$15:A000 - $15:BFFF||$32D||$1D:A000 - $1D:BFFF
|-
|$12E||$0D:C000 - $0D:DFFF||$22E||$15:C000 - $15:DFFF||$32E||$1D:C000 - $1D:DFFF
|-
|$12F||$0D:E000 - $0D:FFFF||$22F||$15:E000 - $15:FFFF||$32F||$1D:E000 - $1D:FFFF
|-
|$130||$0E:0000 - $0E:1FFF||$230||$16:0000 - $16:1FFF||$330||$1E:0000 - $1E:1FFF
|-
|$131||$0E:2000 - $0E:3FFF||$231||$16:2000 - $16:3FFF||$331||$1E:2000 - $1E:3FFF
|-
|$132||$0E:4000 - $0E:5FFF||$232||$16:4000 - $16:5FFF||$332||$1E:4000 - $1E:5FFF
|-
|$133||$0E:6000 - $0E:7FFF||$233||$16:6000 - $16:7FFF||$333||$1E:6000 - $1E:7FFF
|-
|$134||$0E:8000 - $0E:9FFF||$234||$16:8000 - $16:9FFF||$334||$1E:8000 - $1E:9FFF
|-
|$135||$0E:A000 - $0E:BFFF||$235||$16:A000 - $16:BFFF||$335||$1E:A000 - $1E:BFFF
|-
|$136||$0E:C000 - $0E:DFFF||$236||$16:C000 - $16:DFFF||$336||$1E:C000 - $1E:DFFF
|-
|$137||$0E:E000 - $0E:FFFF||$237||$16:E000 - $16:FFFF||$337||$1E:E000 - $1E:FFFF
|-
|$138||$0F:0000 - $0F:1FFF||$238||$17:0000 - $17:1FFF||$338||$1F:0000 - $1F:1FFF
|-
|$139||$0F:2000 - $0F:3FFF||$239||$17:2000 - $17:3FFF||$339||$1F:2000 - $1F:3FFF
|-
|$13A||$0F:4000 - $0F:5FFF||$23A||$17:4000 - $17:5FFF||$33A||$1F:4000 - $1F:5FFF
|-
|$13B||$0F:6000 - $0F:7FFF||$23B||$17:6000 - $17:7FFF||$33B||$1F:6000 - $1F:7FFF
|-
|$13C||$0F:8000 - $0F:9FFF||$23C||$17:8000 - $17:9FFF||$33C||$1F:8000 - $1F:9FFF
|-
|$13D||$0F:A000 - $0F:BFFF||$23D||$17:A000 - $17:BFFF||$33D||$1F:A000 - $1F:BFFF
|-
|$13E||$0F:C000 - $0F:DFFF||$23E||$17:C000 - $17:DFFF||$33E||$1F:C000 - $1F:DFFF
|-
|$13F||$0F:E000 - $0F:FFFF||$23F||$17:E000 - $17:FFFF||$33F||$1F:E000 - $1F:FFFF
|}

Memory Management

2026-02-21T17:30:53Z

WF: /* Memory Block Tables */ Fixing memory block tables

== Overview ==
The F256 series comes with 512KB or 2MB of SRAM, and 512 KB of internal system flash memory. Up to 256 KB additional Memory, either RAM or Flash, can be added through the [[Expansion Port]].
{| class="wikitable"
|+F256 Series Memory Capabilities
!Model
!Hardware CPU
!SRAM
!Flash
!Expansion Port
!DRAM
|-
|F256Jr
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256K
|65C02
|512kB (512k×8)
|512kB
|256kB
|—
|-
|F256Jr2
|65816
|2MB (1M×16)
|512kB
|256kB
|—
|-
|F256K2
|65816
|2MB (1M×16)
|512kB
|256kB
|128MB (not yet supported)
|}
The 1st gen 65c02 systems have an 8-bit data bus and a 16-bit CPU address bus, with an MMU managing 8 × 8k banks to address 512kB RAM plus flash, expansion, and the IO pages.

The 2nd gen 2MB 65816 systems have 16-bit wide SRAMs, enabling higher bandwidth through the FPGA, even though the processor still has an 8-bit wide data bus. The same 64k address MMU with 512kB RAM configuration is used, but the Core2x FPGA core released in the summer of 2025 can enable 24 bit (16 MB) addressing and the full 2MB of SRAM both flat & banked.

A FPGA-based 6809 CPU can be optionally run on all F256 models which will also use this same MMU, and disable the hardware CPU. A 68k FPGA-based processor core is also coming, which should use flat memory addressing only.

'''NOTE:''' Changes associated with Core2x will be in ''italics and underlined'' throughout this page.

== Flat Memory Models ==
Core2x is the future standard FPGA load, with both 24-bit flat access and MMU 8k pages in bank 0. This allows for backwards compatibility, banking direct page and stack, as well as having separate chunks of memory visible in a single CPU-addressable bank for copying & other processing.

The 'e' FPGA load for series 2 provides this same 65816 flat memory model, with the older 1x speed & graphics capabilities. It hasn't been used much yet.
{| class="wikitable"
!Address
!Size
!Description
|-
|$00:0000 - $00:FEFF
|64k - 256
|Core2x: 8×8kB MMU banked
F256K2e: SRAM
|-
|$00:FF00 - $00:FFFF
|256
|Mirror of the last page of Flash, for boot purposes
|-
|$01:0000 - $1F:FFFF
|2M - 64k
|Rest of SRAM*
|-
|$20:0000 - $9F:FFFF
|8M
|DDR3 window (to be implemented?)
|-
|$F0:0000 - $F0:BFFF
|64k reserved
|[[IO Pages]]*
|-
|$F4:0000 - $F7:FFFF
|256k
|Cartridge*
|-
|$F8:0000 - $FF:FFFF
|512k
|Internal Flash*
|}
'''* NOTE:''' In Core2x, the starred regions must have a MMU bit enabled to expose them to the 24-bit flat address. They are only mapped through the MMU by default at boot.

== Memory Management Unit (MMU) ==

=== 8kB Block Layout ===
The MMU splits the 64kB address space into 8 visible slots of 8kB each. A theoretical max of 256 selectable 8kB blocks yields a 2MB address space, which maps 512kB RAM, flash, and expansion.

The Core2x MMU expands the bank numbers to 10 bits, repeating the original layout 4 times, to expose all 2MB of SRAM while remaining backwards compatible.

IO pages have their own space of numbered banks that overlay one fixed slot (6, $C000-$DFFF).
{| class="wikitable"
|+Memory Mapping
!MMU 8kB Block Number!!Purpose
!Flat memory flag
|-
|$00 - $3F||512K SRAM ''(Page 0)''
|
|-
|$40 - $7F||512K System Flash
|''MOVE_FLASH''
|-
|$80 - $9F||256K Cartridge
|''MOVE_FLASH''
|-
|$A0 - $FF||Reserved
|
|-
! colspan="3" |''Core2x expansion''
|-
|$100 - $13F
|512K SRAM Page 1
|SRAM_EN
|-
|$140 - $1FF
|Mirror of Flash, Cart, Reserved
|
|-
|$200 - $23F
|512K SRAM Page 2
|SRAM_EN
|-
|$240 - $2FF
|Mirror of Flash, Cart, Reserved
|
|-
|$300 - $33F
|512K SRAM Page 3
|SRAM_EN
|-
|$340 - $3FF
|Mirror of Flash, Cart, Reserved
|
|}

{| class="wikitable"
|+Final MMU Address Construction
!''22''
!''21''
!20
!19
!18
!17
!16
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
| colspan="10" |MMU Block Number
| colspan="13" rowspan="2" |Byte offset in 8k block
|-
| colspan="2" |''Expansion''
| colspan="2" |Device
| colspan="6" |Block number in device
|}
Device = SRAM, Flash, Cartridge, or Reserved

=== Configuring the MMU ===
There are 4 separate sets of MMU configurations called MLUT 0-3 (Memory Lookup Tables), for easy switching between well-known (including kernel vs user) memory mapping states. Each MLUT holds 8 bank selections, one for each 8kB memory slot respectively. IO mapping is optional, independent of MLUT selection, and overrides slot 6 at $C000.

Only one MLUT is active at any one time. To select the active MLUT, the lower two bits of address $0000 (MMU_MEM_CTRL) are used.

Editing of MLUTs is also controlled by MMU_MEM_CTRL ($0000): Bits 4 and 5 determine which MLUT to be edited, independent of which MLUT is active. Bit 7 has to be set to 1 to enable editing. When editing is enabled, the block number of a physical memory area can be written to the slot register address to map that area to the address in CPU address space. If editing is not enabled (bit 7 of $0000 is 0), the slot register addresses act as ordinary memory with no side effect.
{| class="wikitable"
|+Static MMU Registers
!Address
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$0000
|RW
|MMU_MEM_CTRL
|EDIT_EN
| -
| colspan="2" |EDIT_LUT
|''SRAM_EN''
| -
| colspan="2" |ACT_LUT
|-
|$0001
|RW
|MMU_IO_CTRL
| -
|''SPR_SEL''
|''MOVE_FLASH''
|''MOVE_IO''
|''IO_PAGE_EXT''
|IO_DISABLE
| colspan="2" |IO_PAGE
|}
'''ACT_LUT''': These two bits specify which MLUT (0–3) is used to translate CPU bus address to system bus addresses.

'''EDIT_LUT''': Selects which MLUT (0-3) will be edited.

'''EDIT_EN''': If set (1), this bit enables MLUT editing, and memory addresses $0008–$000F (''and $0002-$0003'') will be used to edit the selected '''EDIT_LUT'''. If clear (0), those memory locations will be standard memory locations and will be mapped like the rest of slot 0.

'''IO_PAGE''': Selects which IO page (0-3) is mapped to slot 6, when not disabled with '''IO_DISABLE'''.

'''IO_DISABLE''': If set (1), slot 6 ($C000-$DFFF) is mapped through the active MLUT as normal. If clear (0), slot 6 is mapped to the selected '''IO_PAGE'''.

Note that writing a simple page number to register $0001 easily selects that IO page (including 0) to be visible, although there are also other Core2x entries now as well.

==== Core2x MMU Registers ====
'''''SRAM_EN''''': Enables access to the SRAM pages 1-3 in flat addresses 00:0000 to 1f:0000. Disables MMU 8k bank access to SRAM only. IO and Flash/Cart are affected by their own bits below.

'''''IO_PAGE_EXT''''': Bit 2 of the total IO page number, enabling pages 4 and 5.

'''''MOVE_IO''''': Moves IO pages from MMU access to 24-bit address F0:0000.

'''''MOVE_FLASH''''': Moves Cartridge & Flash addressing from MMU access to flat address F4:0000 and F8:0000.

'''''SPR_SEL''''': Select current Sprite Block in IO Page 0. 0 = Sprite 0-63, 1 = Sprite 64-127.

{| class="wikitable"
|+MLUT Slot Editing Registers (only visible with EDIT_EN enabled)
!Address
!R/W
!MLUT Slot Address
!7
!6
!5
!4
!3
!2
!1
!0
|-
|''$0002''
|
|
| colspan="2" |''Slot 3 [9:8]''
| colspan="2" |''Slot 2 [9:8]''
| colspan="2" |''Slot 1 [9:8]''
| colspan="2" |''Slot 0 [9:8]''
|-
|''$0003''
|
|
| colspan="2" |''Slot 7 [9:8]''
| colspan="2" |''Slot 6 [9:8]''
| colspan="2" |''Slot 5 [9:8]''
| colspan="2" |''Slot 4 [9:8]''
|-
|$0008
|
|$0000 - $1FFF
| colspan="8" |Edit MLUT Slot 0 block number [7:0]
|-
|$0009
|
|$2000 - $3FFF
| colspan="8" |Edit MLUT Slot 1 block number [7:0]
|-
|$000A
|
|$4000 - $5FFF
| colspan="8" |Edit MLUT Slot 2 block number [7:0]
|-
|$000B
|
|$6000 - $7FFF
| colspan="8" |Edit MLUT Slot 3 block number [7:0]
|-
|$000C
|
|$8000 - $9FFF
| colspan="8" |Edit MLUT Slot 4 block number [7:0]
|-
|$000D
|
|$A000 - $BFFF
| colspan="8" |Edit MLUT Slot 5 block number [7:0]
|-
|$000E
|
|$C000 - $DFFF
| colspan="8" |Edit MLUT Slot 6 block number [7:0]
|-
|$000F
|
|$E000 - $FFFF
| colspan="8" |Edit MLUT Slot 7 block number [7:0]
|}
{| class="wikitable"
|+
[[IO Pages|I/O Pages]]
!I/O Page
!B3
!B1
!B0
!MOVE_IO Address
!Purpose
|-
|0
|0
|0
|0
|''$F0:0000 - $F0:1FFF''
|Low level I/O Register (gamma table, Mouse GFX, all IO devices and vicky registers)
|-
|1
|0
|0
|1
|''$F0:2000 - $F0:3FFF''
|Text display font memory and graphic color MLUTs 0,1,2,3
|-
|2
|0
|1
|0
|''$F0:4000 - $F0:5FFF''
|Text display character matrix
|-
|3
|0
|1
|1
|''$F0:6000 - $F0:7FFF''
|Text display color matrix
|-
|''4''
|''1''
|''0''
|''0''
|''$F0:8000 - $F0:9FFF''
|''Memory text Color background LUT 0 & 1, Foreground LUT 0 & 1''
|-
|''5''
|''1''
|''0''
|''1''
|''$F0:A000 - $F0:BFFF''
|''Memory text FONT 0,1,2,3 for 8x8 or 0,1 for 8x16''
|}
{| class="wikitable"
|}

== Memory Block Tables ==
The following table shows which block number has to be written into a slot register to make the each 8 KB block of memory available to the CPU.

Note that since Flash & Expansion are mirrored across all 4 Core2x expansion ranges, MMU blocks $40, $140, $240, $340 all point to the same physical flash, and $80, $180, $280, $380 all point to the same physical expansion addresses.

{| class="wikitable" style="border: none; background: none;"
! colspan="2" scope="col" | RAM
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Flash
| rowspan="66" style="border: none; background: none;" |
! colspan="2" scope="col" | Expansion
|-
! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address

! scope="col" | Block Number
! scope="col" | Flat Address
|-
|$00||$00:0000 - $00:1FFF||$40||$F8:0000 - $F8:1FFF||$80||$F4:0000 - $F4:1FFF
|-
|$01||$00:2000 - $00:3FFF||$41||$F8:2000 - $F8:3FFF||$81||$F4:2000 - $F4:3FFF
|-
|$02||$00:4000 - $00:5FFF||$42||$F8:4000 - $F8:5FFF||$82||$F4:4000 - $F4:5FFF
|-
|$03||$00:6000 - $00:7FFF||$43||$F8:6000 - $F8:7FFF||$83||$F4:6000 - $F4:7FFF
|-
|$04||$00:8000 - $00:9FFF||$44||$F8:8000 - $F8:9FFF||$84||$F4:8000 - $F4:9FFF
|-
|$05||$00:A000 - $00:BFFF||$45||$F8:A000 - $F8:BFFF||$85||$F4:A000 - $F4:BFFF
|-
|$06||$00:C000 - $00:DFFF||$46||$F8:C000 - $F8:DFFF||$86||$F4:C000 - $F4:DFFF
|-
|$07||$00:E000 - $00:FFFF||$47||$F8:E000 - $F8:FFFF||$87||$F4:E000 - $F4:FFFF
|-
|$08||$01:0000 - $01:1FFF||$48||$F9:0000 - $F9:1FFF||$88||$F5:0000 - $F5:1FFF
|-
|$09||$01:2000 - $01:3FFF||$49||$F9:2000 - $F9:3FFF||$89||$F5:2000 - $F5:3FFF
|-
|$0A||$01:4000 - $01:5FFF||$4A||$F9:4000 - $F9:5FFF||$8A||$F5:4000 - $F5:5FFF
|-
|$0B||$01:6000 - $01:7FFF||$4B||$F9:6000 - $F9:7FFF||$8B||$F5:6000 - $F5:7FFF
|-
|$0C||$01:8000 - $01:9FFF||$4C||$F9:8000 - $F9:9FFF||$8C||$F5:8000 - $F5:9FFF
|-
|$0D||$01:A000 - $01:BFFF||$4D||$F9:A000 - $F9:BFFF||$8D||$F5:A000 - $F5:BFFF
|-
|$0E||$01:C000 - $01:DFFF||$4E||$F9:C000 - $F9:DFFF||$8E||$F5:C000 - $F5:DFFF
|-
|$0F||$01:E000 - $01:FFFF||$4F||$F9:E000 - $F9:FFFF||$8F||$F5:E000 - $F5:FFFF
|-
|$10||$02:0000 - $02:1FFF||$50||$FA:0000 - $FA:1FFF||$90||$F6:0000 - $F6:1FFF
|-
|$11||$02:2000 - $02:3FFF||$51||$FA:2000 - $FA:3FFF||$91||$F6:2000 - $F6:3FFF
|-
|$12||$02:4000 - $02:5FFF||$52||$FA:4000 - $FA:5FFF||$92||$F6:4000 - $F6:5FFF
|-
|$13||$02:6000 - $02:7FFF||$53||$FA:6000 - $FA:7FFF||$93||$F6:6000 - $F6:7FFF
|-
|$14||$02:8000 - $02:9FFF||$54||$FA:8000 - $FA:9FFF||$94||$F6:8000 - $F6:9FFF
|-
|$15||$02:A000 - $02:BFFF||$55||$FA:A000 - $FA:BFFF||$95||$F6:A000 - $F6:BFFF
|-
|$16||$02:C000 - $02:DFFF||$56||$FA:C000 - $FA:DFFF||$96||$F6:C000 - $F6:DFFF
|-
|$17||$02:E000 - $02:FFFF||$57||$FA:E000 - $FA:FFFF||$97||$F6:E000 - $F6:FFFF
|-
|$18||$03:0000 - $03:1FFF||$58||$FB:0000 - $FB:1FFF||$98||$F7:0000 - $F7:1FFF
|-
|$19||$03:2000 - $03:3FFF||$59||$FB:2000 - $FB:3FFF||$99||$F7:2000 - $F7:3FFF
|-
|$1A||$03:4000 - $03:5FFF||$5A||$FB:4000 - $FB:5FFF||$9A||$F7:4000 - $F7:5FFF
|-
|$1B||$03:6000 - $03:7FFF||$5B||$FB:6000 - $FB:7FFF||$9B||$F7:6000 - $F7:7FFF
|-
|$1C||$03:8000 - $03:9FFF||$5C||$FB:8000 - $FB:9FFF||$9C||$F7:8000 - $F7:9FFF
|-
|$1D||$03:A000 - $03:BFFF||$5D||$FB:A000 - $FB:BFFF||$9D||$F7:A000 - $F7:BFFF
|-
|$1E||$03:C000 - $03:DFFF||$5E||$FB:C000 - $FB:DFFF||$9E||$F7:C000 - $F7:DFFF
|-
|$1F||$03:E000 - $03:FFFF||$5F||$FB:E000 - $FB:FFFF||$9F||$F7:E000 - $F7:FFFF
|-
|$20||$04:0000 - $04:1FFF||$60||$FC:0000 - $FC:1FFF
|
|
|-
|$21||$04:2000 - $04:3FFF||$61||$FC:2000 - $FC:3FFF
|
|-
|$22||$04:4000 - $04:5FFF||$62||$FC:4000 - $FC:5FFF
|-
|$23||$04:6000 - $04:7FFF||$63||$FC:6000 - $FC:7FFF
|-
|$24||$04:8000 - $04:9FFF||$64||$FC:8000 - $FC:9FFF
|-
|$25||$04:A000 - $04:BFFF||$65||$FC:A000 - $FC:BFFF
|-
|$26||$04:C000 - $04:DFFF||$66||$FC:C000 - $FC:DFFF
|-
|$27||$04:E000 - $04:FFFF||$67||$FC:E000 - $FC:FFFF
|-
|$28||$05:0000 - $05:1FFF||$68||$FD:0000 - $FD:1FFF
|-
|$29||$05:2000 - $05:3FFF||$69||$FD:2000 - $FD:3FFF
|-
|$2A||$05:4000 - $05:5FFF||$6A||$FD:4000 - $FD:5FFF
|-
|$2B||$05:6000 - $05:7FFF||$6B||$FD:6000 - $FD:7FFF
|-
|$2C||$05:8000 - $05:9FFF||$6C||$FD:8000 - $FD:9FFF
|-
|$2D||$05:A000 - $05:BFFF||$6D||$FD:A000 - $FD:BFFF
|
|-
|$2E||$05:C000 - $05:DFFF||$6E||$FD:C000 - $FD:DFFF
|
|-
|$2F||$05:E000 - $05:FFFF||$6F||$FD:E000 - $FD:FFFF
|-
|$30||$06:0000 - $06:1FFF||$70||$FE:0000 - $FE:1FFF
|-
|$31||$06:2000 - $06:3FFF||$71||$FE:2000 - $FE:3FFF
|-
|$32||$06:4000 - $06:5FFF||$72||$FE:4000 - $FE:5FFF
|-
|$33||$06:6000 - $06:7FFF||$73||$FE:6000 - $FE:7FFF
|-
|$34||$06:8000 - $06:9FFF||$74||$FE:8000 - $FE:9FFF
|-
|$35||$06:A000 - $06:BFFF||$75||$FE:A000 - $FE:BFFF
|-
|$36||$06:C000 - $06:DFFF||$76||$FE:C000 - $FE:DFFF
|-
|$37||$06:E000 - $06:FFFF||$77||$FE:E000 - $FE:FFFF
|-
|$38||$07:0000 - $07:1FFF||$78||$FF:0000 - $FF:1FFF
|-
|$39||$07:2000 - $07:3FFF||$79||$FF:2000 - $FF:3FFF
|-
|$3A||$07:4000 - $07:5FFF||$7A||$FF:4000 - $FF:5FFF
|-
|$3B||$07:6000 - $07:7FFF||$7B||$FF:6000 - $FF:7FFF
|-
|$3C||$07:8000 - $07:9FFF||$7C||$FF:8000 - $FF:9FFF
|-
|$3D||$07:A000 - $07:BFFF||$7D||$FF:A000 - $FF:BFFF
|-
|$3E||$07:C000 - $07:DFFF||$7E||$FF:C000 - $FF:DFFF
|
|-
|$3F||$07:E000 - $07:FFFF||$7F||$FF:E000 - $FF:FFFF
|}

For Core2x extended map 65816 core:
{| class="wikitable" style="border: none; background: none;"
! colspan=2 scope=col| ''512K SRAM Page 1''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 2''
| rowspan=66 style="border: none; background: none;" |
! colspan=2 scope=col| ''512K SRAM Page 3''
|-
! scope=col | Block Number
! scope=col | Physical Address

! scope=col | Block Number
! scope=col | Physical Address

! scope=col | Block Number
! scope=col | Physical Address
|-
|$100||$20:0000 - $20:1FFF||$200||$40:0000 - $40:1FFF||$300||$60:0000 - $60:1FFF
|-
|$101||$20:2000 - $20:3FFF||$201||$40:2000 - $40:3FFF||$301||$60:2000 - $60:3FFF
|-
|$102||$20:4000 - $20:5FFF||$202||$40:4000 - $40:5FFF||$302||$60:4000 - $60:5FFF
|-
|$103||$20:6000 - $20:7FFF||$203||$40:6000 - $40:7FFF||$303||$60:6000 - $60:7FFF
|-
|$104||$20:8000 - $20:9FFF||$204||$40:8000 - $40:9FFF||$304||$60:8000 - $60:9FFF
|-
|$105||$20:A000 - $20:BFFF||$205||$40:A000 - $40:BFFF||$305||$60:A000 - $60:BFFF
|-
|$106||$20:C000 - $20:DFFF||$206||$40:C000 - $40:DFFF||$306||$60:C000 - $60:DFFF
|-
|$107||$20:E000 - $20:FFFF||$207||$40:E000 - $40:FFFF||$307||$60:E000 - $60:FFFF
|-
|$108||$21:0000 - $21:1FFF||$208||$41:0000 - $41:1FFF||$308||$61:0000 - $61:1FFF
|-
|$109||$21:2000 - $21:3FFF||$209||$41:2000 - $41:3FFF||$309||$61:2000 - $61:3FFF
|-
|$10A||$21:4000 - $21:5FFF||$20A||$41:4000 - $41:5FFF||$30A||$61:4000 - $61:5FFF
|-
|$10B||$21:6000 - $21:7FFF||$20B||$41:6000 - $41:7FFF||$30B||$61:6000 - $61:7FFF
|-
|$10C||$21:8000 - $21:9FFF||$20C||$41:8000 - $41:9FFF||$30C||$61:8000 - $61:9FFF
|-
|$10D||$21:A000 - $21:BFFF||$20D||$41:A000 - $41:BFFF||$30D||$61:A000 - $61:BFFF
|-
|$10E||$21:C000 - $21:DFFF||$20E||$41:C000 - $41:DFFF||$30E||$61:C000 - $61:DFFF
|-
|$10F||$21:E000 - $21:FFFF||$20F||$41:E000 - $41:FFFF||$30F||$61:E000 - $61:FFFF
|-
|$110||$22:0000 - $22:1FFF||$210||$42:0000 - $42:1FFF||$310||$62:0000 - $62:1FFF
|-
|$111||$22:2000 - $22:3FFF||$211||$42:2000 - $42:3FFF||$311||$62:2000 - $62:3FFF
|-
|$112||$22:4000 - $22:5FFF||$212||$42:4000 - $42:5FFF||$312||$62:4000 - $62:5FFF
|-
|$113||$22:6000 - $22:7FFF||$213||$42:6000 - $42:7FFF||$313||$62:6000 - $62:7FFF
|-
|$114||$22:8000 - $22:9FFF||$214||$42:8000 - $42:9FFF||$314||$62:8000 - $62:9FFF
|-
|$115||$22:A000 - $22:BFFF||$215||$42:A000 - $42:BFFF||$315||$62:A000 - $62:BFFF
|-
|$116||$22:C000 - $22:DFFF||$216||$42:C000 - $42:DFFF||$316||$62:C000 - $62:DFFF
|-
|$117||$22:E000 - $22:FFFF||$217||$42:E000 - $42:FFFF||$317||$62:E000 - $62:FFFF
|-
|$118||$23:0000 - $23:1FFF||$218||$43:0000 - $43:1FFF||$318||$63:0000 - $63:1FFF
|-
|$119||$23:2000 - $23:3FFF||$219||$43:2000 - $43:3FFF||$319||$63:2000 - $63:3FFF
|-
|$11A||$23:4000 - $23:5FFF||$21A||$43:4000 - $43:5FFF||$31A||$63:4000 - $63:5FFF
|-
|$11B||$23:6000 - $23:7FFF||$21B||$43:6000 - $43:7FFF||$31B||$63:6000 - $63:7FFF
|-
|$11C||$23:8000 - $23:9FFF||$21C||$43:8000 - $43:9FFF||$31C||$63:8000 - $63:9FFF
|-
|$11D||$23:A000 - $23:BFFF||$21D||$43:A000 - $43:BFFF||$31D||$63:A000 - $63:BFFF
|-
|$11E||$23:C000 - $23:DFFF||$21E||$43:C000 - $43:DFFF||$31E||$63:C000 - $63:DFFF
|-
|$11F||$23:E000 - $23:FFFF||$21F||$43:E000 - $43:FFFF||$31F||$63:E000 - $63:FFFF
|-
|$120||$24:0000 - $24:1FFF||$220||$44:0000 - $44:1FFF
|$320
|$64:0000 - $64:1FFF
|-
|$121||$24:2000 - $24:3FFF||$221||$44:2000 - $44:3FFF
|$321
|$64:2000 - $64:3FFF
|-
|$122||$24:4000 - $24:5FFF||$222||$44:4000 - $44:5FFF
|$322
|$64:4000 - $64:5FFF
|-
|$123||$24:6000 - $24:7FFF||$223||$44:6000 - $44:7FFF
|$323
|$64:6000 - $64:7FFF
|-
|$124||$24:8000 - $24:9FFF||$224||$44:8000 - $44:9FFF
|$324
|$64:8000 - $64:9FFF
|-
|$125||$24:A000 - $24:BFFF||$225||$44:A000 - $44:BFFF
|$325
|$64:A000 - $64:BFFF
|-
|$126||$24:C000 - $24:DFFF||$226||$44:C000 - $44:DFFF
|$326
|$64:C000 - $64:DFFF
|-
|$127||$24:E000 - $24:FFFF||$227||$44:E000 - $44:FFFF
|$327
|$64:E000 - $64:FFFF
|-
|$128||$25:0000 - $25:1FFF||$228||$45:0000 - $45:1FFF
|$328
|$65:0000 - $65:1FFF
|-
|$129||$25:2000 - $25:3FFF||$229||$45:2000 - $45:3FFF
|$329
|$65:2000 - $65:3FFF
|-
|$12A||$25:4000 - $25:5FFF||$22A||$45:4000 - $45:5FFF
|$32A
|$65:4000 - $65:5FFF
|-
|$12B||$25:6000 - $25:7FFF||$22B||$45:6000 - $45:7FFF
|$32B
|$65:6000 - $65:7FFF
|-
|$12C||$25:8000 - $25:9FFF||$22C||$45:8000 - $45:9FFF
|$32C
|$65:8000 - $65:9FFF
|-
|$12D||$25:A000 - $25:BFFF||$22D||$45:A000 - $45:BFFF
|$32D
|$65:A000 - $65:BFFF
|-
|$12E||$25:C000 - $25:DFFF||$22E||$45:C000 - $45:DFFF
|$32E
|$65:C000 - $65:DFFF
|-
|$12F||$25:E000 - $25:FFFF||$22F||$45:E000 - $45:FFFF
|$32F
|$65:E000 - $65:FFFF
|-
|$130||$26:0000 - $26:1FFF||$230||$46:0000 - $46:1FFF
|$330
|$66:0000 - $66:1FFF
|-
|$131||$26:2000 - $26:3FFF||$231||$46:2000 - $46:3FFF
|$331
|$66:2000 - $66:3FFF
|-
|$132||$26:4000 - $26:5FFF||$232||$46:4000 - $46:5FFF
|$332
|$66:4000 - $66:5FFF
|-
|$133||$26:6000 - $26:7FFF||$233||$46:6000 - $46:7FFF
|$333
|$66:6000 - $66:7FFF
|-
|$134||$26:8000 - $26:9FFF||$234||$46:8000 - $46:9FFF
|$334
|$66:8000 - $66:9FFF
|-
|$135||$26:A000 - $26:BFFF||$235||$46:A000 - $46:BFFF
|$335
|$66:A000 - $66:BFFF
|-
|$136||$26:C000 - $26:DFFF||$236||$46:C000 - $46:DFFF
|$336
|$66:C000 - $66:DFFF
|-
|$137||$26:E000 - $26:FFFF||$237||$46:E000 - $46:FFFF
|$337
|$66:E000 - $66:FFFF
|-
|$138||$27:0000 - $27:1FFF||$238||$47:0000 - $47:1FFF
|$338
|$67:0000 - $67:1FFF
|-
|$139||$27:2000 - $27:3FFF||$239||$47:2000 - $47:3FFF
|$339
|$67:2000 - $67:3FFF
|-
|$13A||$27:4000 - $27:5FFF||$23A||$47:4000 - $47:5FFF
|$33A
|$67:4000 - $67:5FFF
|-
|$13B||$27:6000 - $27:7FFF||$23B||$47:6000 - $47:7FFF
|$33B
|$67:6000 - $67:7FFF
|-
|$13C||$27:8000 - $27:9FFF||$23C||$47:8000 - $47:9FFF
|$33C
|$67:8000 - $67:9FFF
|-
|$13D||$27:A000 - $27:BFFF||$23D||$47:A000 - $47:BFFF
|$33D
|$67:A000 - $67:BFFF
|-
|$13E||$27:C000 - $27:DFFF||$23E||$47:C000 - $47:DFFF
|$33E
|$67:C000 - $67:DFFF
|-
|$13F||$27:E000 - $27:FFFF||$23F||$47:E000 - $47:FFFF
|$33F
|$67:E000 - $67:FFFF
|}

WF16 Video Architecture

2026-02-21T05:48:45Z

WF: /* Tiles */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''F256'''
|1024
|888
|4×256
|0-3
|0-3
|No 4bpp, this is all 8bpp
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|666
|256×16
|—
|0-255
|Everything is sprites. RGB channels share low bit, 5551 = 16 bits
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''F256'''
|—
|—
|—
| colspan="2" |Palette (0-3)
| colspan="3" |Tileset (0-7)
| colspan="8" |Tile (0-255)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

FPU Accumulator

2026-02-20T09:14:52Z

WF:

WF16 Video Architecture

2026-02-20T06:49:57Z

WF: /* Global settings */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth, which should on its own be feasible.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256K'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

Emulation

2026-02-20T06:49:15Z

WF: /* Foenijs */

== FoenixIDE ==
The FoenixIDE provides emulation of various Foenix Retro Systems including,
{| class="wikitable"
|+
!System
!Descripton
|-
|F256K(816)
|The F256K computer with integrated keyboard and WDC65C816 processor.
|-
|F256K
|The F256K computer with integrated keyboard and WDC65C02 processor.
|-
|Jr(816)
|The F256 Jr. computer with a WDC65C816 processor.
|-
|Jr
|The F256 Jr. computer with a WDC65C02 processor.
|-
|U+
|The C256 Foenix U+ (4Meg RAM Config) - Legacy
|-
|U
|The C256 Foenix U (2Meg RAM Config) - Legacy
|-
|C
|The C256 Foenix FMX - Legacy
|-
|B
|The C256 Foenix (original) - Legacy
|}

=== Installation ===
The current Windows installation file (FoenixIDE.Setup.msi) and source code can be found here,
'''https://github.com/Trinity-11/FoenixIDE/releases'''

== Foenijs ==
Runs in your browser with no setup.

https://www.white-flame.com/foenijs/, Wiki page [[Foenijs]]

* Supports the F256 line (Jr, Jr2, K, K2), with 65c02 and 65816
* All graphics modes & features
* All audio chips (still some rough edges)
* PS/2 mouse, PS/2 keyboard, and built-in K keyboard emulation
* NES/SNES via USB gamepads, Atari joystick via keyboard.
* SD Card images are persistently stored in your browser's IndexedDB
** Card library, with full card image upload/download, and new formatted image creation
** Individual file transfers directly to/from card images
** 1-click program launch
* Strong CPU, stack, and device debugging support, with live views for memory and individual graphics data.
* Directly run a program or mount a card by adding URL parameters
** <code>url=http://...</code> to a <code>pgz</code>/<code>pgx</code>/<code>bas</code> program, or <code>bin</code>/<code>iso</code>/<code>img</code> card image with optional <code>.gz</code> or <code>.zip</code>.
*** Github links automatically rewrite to their <code>raw.githubusercontent.com</code> form to get around CORS issues.
** <code>run=filename</code> to autorun a file within a card image URL
** <code>model=f256jr</code>, <code>f256jr2</code>, <code>f256k</code>, or <code>f256k2</code>
** Formatted as e.g. <code><nowiki>https://www.white-flame.com/foenijs/?url=...&model=</nowiki>...</code>

TODO:

* Core2x and 6809
* Better Atari joystick support
* Networking
* K2 optical keyboard
* Cartridges
* Hardware I/O ports: debug ports, IEC port, DIP switches, MIDI ports

[https://discord.com/channels/691915291721990194/1455809214231478414 Discord support channel] on the Wildbits server, with the author wf2. Feature requests are welcomed.

== MAME ==
This emulator is currently under development (23 Mar 2025). See here: https://github.com/dtremblay/mame

Releases are published in GitHub and announced in Discord: https://discord.com/channels/691915291721990194/1330998392481906768

(a work-in-progress sdcard .img file containing many games, tools and media files prepared in March 2025 can be found here: https://github.com/Mu0n/F256MiscGoodies/tree/main/SDCard_Collection consult the readme of that page to get the right file)

MAME is available for Linux, Mac and Windows. Future development of the F256 machines will support the 65816, 6809 and 68000 processors.

Currently, only the F256K is partially implemented.

* Memory Management Unit (MMU) at address $0
* SD Card with SPI
* Matrix Keyboard with VIA
* Game Controllers: Atari Joysticks with VIA
* Text display, Sprites, Tiles and Bitmaps (respecting the layers)
* Interrupts: SOF, SOL, RTC, Timers, VIA0, VIA1
* Timers: Real-Time Clock (RTC), Timer0 (at 25Mhz) and Timer1 (at SOF 60 or 70Hz)
* Math processor
* Random Number Generator (RNG)
* Sound Chips: PSG (dual - stereo), OPL, SID (dual - stereo)
* Direct Memory Access (DMA)
Unimplemented features:

* UART (serial port)
* IEC
* CODEC
* NES/SNES Game Controllers
* PS/2 Mouse and Keyboard
* WIFI
* Buzzer and status LEDs
* Debug port
* DIP switches
* External Memory Cartridge

====== How to Run MAME ======
MAME has quite an extensive list of features that can be enabled and disabled.

To run F256K in full screen mode:

<code>./f256 f256k</code>

To run in window mode:

<code>./f256 f256k -window -resolution 800x600</code>

To set a disk image (for the SD Card):

<code>./f256 f256k -harddisk sdcard.img</code>

To disable sound:

<code>./f256 f256k -sound none</code>

To collect logs:

<code>./f256 f256k -log</code>

Within MAME emulator, you can see the frame rate (in percent) by pressing the '''F11''' key.

You can modify settings and key assignments using the '''TAB''' key.

You can see the debug console (to step in CPU memory and view memory values) using the back-tick key '''`'''.

Exit the emulator using the '''ESC''' key.

'''''Note''': all these keys can be modified, so these are the default settings.''

====== Creating an SD Card Image to use in MAME Emulator and Foenix IDE ======
'''Easy Method:'''

You can use the FoenixIDE to write your SD Card to a single ISO file. In the FoenixIDE menu, select '''Tools | Export SD Card to IMG.''' You will then get a Save dialog: pick a filename to save.

'''Hard Method:'''

''These instructions require a Linux Operating System or MinGW.''

Create a blank image of 64 blocks of 1 MB:

<code>dd if=/dev/zero of=sdcard.img bs=1M count=64</code>

Partition the image:

<code>parted sdcard.img --script mklabel msdos</code>

<code>parted sdcard.img --script mkpart primary fat32 1MiB 100%</code>

You need to know the starting sector for the next step. To find the '''starting''' '''sector''': <code>fdisk -l sdcard.img</code>

You'll get something like this:

<code>Device Boot Start End Sectors Size Id Type</code>

<code>sdcard.img1 2048 131071 129024 63M c W95 FAT32 (LBA)</code>

The '''starting sector''' is "2048" in the listing above.

Create a Loop Device for Formatting

Map the partition to a loop device:

<code>sudo losetup -o $((2048 * 512)) --sizelimit $((129024 * 512)) /dev/loop0 sdcard.img</code>

Format it: <code>sudo mkfs.vfat -F 32 /dev/loop0</code>

Detach it: <code>sudo losetup -d /dev/loop0</code>

The disk image is now ready, but it's empty. To copy files into the disk, you need to mount it. After it's mounted, you can copy files to it.

<code>mkdir /mnt/f256</code>

<code>sudo mount -o loop,offset=$((2048 * 512)) sdcard.img /mnt/f256</code>

<code>cp myfile.txt mnt/</code>

<code>sudo umount mnt</code>

WF FPGA Ideas

2026-02-20T06:46:32Z

WF: /* Bitstream readers/writers */

== Video enhancements ==
[[WF16 Video Architecture]]

== Math coprocessor ==
[[FPU Accumulator]]

== SDCard ==
Auto-tx on read. Could supersede this with auto-reading a 16-bit length to a storage pointer, running in the background, flag or interrupt when done. Loading straight into DDR3 would be good once audio/video can read from there.

Stream MP3 or MIDI file from disk (or ddr3?) straight to chips

== Bootstrap and Machine Identity ==
Access to the cores SDCard. Name something better than the current hardcoded names.

Soft-boot into one of the other cores, instead of relying on jumpers to select the core. Have an extended PGZ header or new file format that can request such things. Note that PGZ should say how many and which 8k blocks or 64k banks it's hardcoded for. Should be another load format for "play nice" system tools that can be simultaneously loaded.

Identify cores by an 8 character ASCII string, instead of bit fields. Maybe have a version number (16 bit) per release of any named platform.

Have different ROM loads for different cores? Or boot from RAM if some magic bytes occur there instead of ROM., though that would be part of the ROM boot that can do that, what ISA would the code be?

RP2040 uses the Slave SelectMAX x8 config interface of the FPGA, and its 8 data pins should be GPIO for the FPGA to talk back to the RP after it's up and running (unless the pins are used for something else). The RP software needs updating for that.

Simplest comms would be splitting the 8-bit path into two 4-bit independent directional channels. Clock (toggle when new data is sent), Ack (receiver toggles when it's read), 2 data bits. All polled on the software end. The RP2040 could be crunching FAT32 stuff while the FPGA is waiting to write to it, no problem.

SRAM can be retained between resets:

<code>char my_crash_info[100] __attribute__((section(".uninitialized_data")));</code>

and with a macro:

<code>#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group</code>

<code>datetime_t __uninitialized_ram(persist_date);</code>

=== Tentatively Proposed RP2040 Startup ===

* Read SD Card for magic <code>/MYCORE.TXT</code> file containing the full path of the core filename to boot.
** If this exists, DIP switches can be some form of override. Need to be able to break in if something messes up. On configuring MYCORE, always tell the user to set their DIP switches to 00.
** If this doesn't exist, oldsk00l DIP switches determine the core to boot.
* Load compressed core file from card and get the FPGA going.
** Set the FPGA comm handshake pins to 0 before releasing the init/reset command to the FPGA.
* Load <code>/RPLIB</code> library and jump into it, if exists (else infinite loop). This runs whatever library functionality can talk to the FPGA, and is upgradable as a file through the loaded utilities.
The library should have functions to browse the cores sdcard, and select which file to boot with.

TODO - do the core selection DIP pins also hit the FPGA for flash banking? If so, then we might not be able to escape them.

== Timers ==
Ensure that the 24-bit value latches when the LSB is read (or the MSB is written?) for consistent reads.

== Wavetable Audio ==
Some form of wavetable audio is sorely missing for Amiga, TG16, SNES, Soundblaster era audio, especially sound effects. Basic multiple channels of stereo or panned mono, uncompressed samples, support some simple compression formats.

Pull small buffers of audio into the FPGA from RAM, keep 2 live at a time, one playing, one buffered. At 25MHz with a 48KHz sample rate, 1 sample lasts 520 cycles (20µsec), could be fast enough to fetch while the last sample is playing and just single-buffer it? Or even a rolling window Should also support just-in-time software generation of each buffer, with IRQ notifications.

Stretch samples to whatever the output sampling rate is. Linear interpolation would be neat, but probably optional. Same with the decay-to-zero that many old synth chips had.

== Sound Chip Instances ==
Instead of duplicating hardware instances of sound chips, multiplex all their registers and internal variables. Access would select 1 of them, and the hardware would run with that multiplexer active on all its values. Compare the size taken, depends on how complex the chip is.

Since sound chips don't need to be that fast, serially looping through and executing a cycle, accumulating their output, for the final audio sample would be fine. Some of them do this internally with their voices anyway.

Register to select which instance(s) to use, so programs can be agnostic to what sound context exists with other things. Probably expose 2 chips at a time through the IO registers, with a separate one to select which bank of 2 to use. At least for mono chips, or those which are commonly in pairs. Stereo chips could just have 1 register set exposed.

== 65816 support ==
Remap page 0 into any 64kB bank, allowing direct page, stack, etc, to have its own swappable space. However, need to consider how this goes for interrupts. An interrupt will probably have to remap to hardware bank 0, but then somehow restore the bank that used to be there. Keeping the upper 256 bytes locked somewhere (flash or bank 0 RAM) would solve that. The 8kB MMU can be used for these purposes already, but I wonder if the full bank swapping might be easier, but likely not really necessary as long as the MMU is around.

== FPGA-based CPU ==
65816 but with a genuine 16-bit data bus.

Keep 6809 in the same core with the 65816 running. Switch between either at any time (bus master), or alternate cycles. At core2x speed, they could each run at 6MHz alternately hitting the SRAM.

If the bus can be more dynamic, especially during vblank/hblank, the CPUs can run a lot faster there.

== Bitstream readers/writers ==
Write a byte or word to a FPGA location, it takes a CPU cycle to write it, and bumps its pointer.

For a bit stream, a 32-bit bitpointer covers 4Gb = 512MB. A write would need to know the width to write. Maybe 16 registers, write a value to one of those to declare how many bits from the written value to write. This actually allows the index register to determine width dynamically, which is nice. Both read & write interfaces should use this. A complete hack but easier to use would be to have 18 regs. For any width >8 bits, a 2nd access to the next register would grab the high byte, even though it's technically the trigger for the next higher. But this would get confusing in 65816 16-bit mode, accessing lower lengths.

Automatically converts between 32-bit bitstream pointer and 24-bit byte pointer + bit offset. When writing to the byte pointer, it automatically zeros out the bit offset, for easier initialization from standard word boundaries. If loading a bit pointer from normal pointer + bit offset, set the bit offset last.

Separate read & write context, so copies, decompression, etc, can be done. Bit pointers can be directly read/written as well. Direction is always in the positive direction, though, at least for now.

Probably good to support 0-length, for dynamically computed lengths. So with 0-16 supported, that's 17 entry points, kinda messy.

Also, skip forward N bits without a read or write. Technically this could just be a read N bits and ignore the value, but this should be 0-65535 bits skipped. Could also just do a 32-bit add on the pointer register.

8bit interface: 2 bitpointers, then 8 byte locs for pointer 0, and 8 byte locs for pointer 1.

16bit interface: 2 bitpointers, then 16 word locs for pointer 0, 16 word locs for pointer 1. Writes triggered on high byte write. Reads trigger on low byte read, which readies the high byte.

This is a CPU-blocking interface for reads, buffered for writes.

== Optical Keyboard ==
Can this be sent as 9 events of 8bits, instead of 8 events of 9 bits (2 bytes)? However the self-describing row number might be useful to keep.

== RLE Format(s) ==
RLE layers, DMA, and potentially sprites can use RLE encoding.
{| class="wikitable"
|+Span-based RLE formats
!bpp
!Layout
!length
!Max compression
!Breakeven
|-
|1
|<code>clllllll</code>
|1-128
|16:1 byte
|8px
|-
|2
|<code>cc111111</code>
|1-64
|16:1 byte
|4 pixels
|-
|4
|<code>ccccllll</code>
|1-16
|4:1 byte
|2 pixels
|-
|4
|<code>ccccCCCC llllllll llllllll</code>
|1-256
|170:1 byte (512:3)
|3+3 pixels
|-
|8
|<code>cccccccc llllllll</code>
|1-256
|128:1 byte
|2 pixels
|}
However, it would be useful to have spans of literal pixels as well, instead of just solid color span fills.

<code>0lllllll cccccccc</code> = span length L of color C, 0 = transparent

<code>1lllllll cccccccc...</code>= L count of individual pixels

For a bpp less than 8, probably require them to fill an even byte or word count

For now, RLE layers should be simple length + 8bpp aligned words. RLE bitmaps would be something different, maybe it's too flexible so we should just leave that to the CPU. It would save a lot of bandwidth for bitmap overlay layers with large transparent windows, though.

== DMA/Blitter ==
Maybe separate out 2d mode into its own blitter?

Flag to mask out the 'fill/mask' color (default 0)

Clip to output screen dimensions.

Xflip, yflip, maybe 90° rotation, but that means dest dimensions change? Scaling? Full affine transform?

Unpack RLE graphics, for better memory usage. Could still do x/y flip because this isn't raster-dependent. Must know the total x/y though if clipping is supported

Fields:

* bpp (could expand from src to dest given an offset?)
* src w/h/stride
* dest w/h/stride

'''TODO - V2'''

Clipping? Or should the src/dest be handled in software?

Ideally, there'd be a clip bounds defined at the dest address, w, h, stride, bpp. The source address is defined, and it's blitted into an x/y in the dest screen, automatically clipped. This could also be used as a pixel/stamp plotter.

If there end up being a large number of parameters for a src or dest, it would be nice to have multiple profiles. Either read src/dest profiles from ram, or have say 4 src & 4 dests saved, and blit from src N to dest M.

RLE graphics should probably save their w/h and mode implicitly as the first 2 words, as they are their own free-form shapes.

Since DMA currently only takes place during VBLANK, could be more efficient to have a DMA list to run when VSYNC hits, blasting those out as fast as possible.

For 1bpp (or maybe others, too?) and/or/nor/nand/xor modes would be necessary.

WF16 Video Architecture

2026-02-20T06:45:43Z

WF: /* Global settings */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz.
{| class="wikitable"
!
!Dot clock
!HDMI Serializer
|-
|640x480
|25.175 MHz
|125.875 MHz
|-
|960x540
|37.125 MHz
|186.625 MHz
|}
Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256K'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-02-20T06:37:17Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256K'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
Since transparency doesn't work well with a separate sprite line buffer, I wonder how many parallel sprite units could be in wait to be polled per layer for proper stacking of transparency. These would be similar to shift registers, but basically just a word cache that can render a pixel given an X coordinate that's asked of it. It would be a priority queue that the topmost one that serves that xcoord could present its pixel, and interest would trickle down and vie for a pull from the sram bus.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

IO Pages

2026-02-20T06:27:20Z

WF: /* $D880: NES/SNES Gamepads */

More detailed information is found in the [[Manuals]].

== Notes ==
'''SRAM Address''': Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

'''BGR''': A 3-byte color entry in Blue, Green, Red order.

'''BGRx''': A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

'''RGB''': A 3-byte color entry in Red, Green, Blue order, as things should be.

== IO Page 0 ==

====== $C000: Gamma Lookup ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|RW
|
|Blue gamma conversion table
|-
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|RW
|
|Green gamma conversion table
|-
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|RW
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
This is currently mirrored 4 times in $CC00 - $CFFF.

===== $D000: VICKY Config =====

====== $D000: Master Control Registers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D000
|$F0:1000
|RW
|MSTR_CTRL_0
|—
|GAMMA
|SPRITE
|TILE
|BITMAP
|GRAPH
|OVRLY
|TEXT
|-
|$D001
|$F0:1001
|RW
|MSTR_CTRL_1
|—
|—
|FON_SET
|FON_OVLY
|MON_SLP
|DBL_Y
|DBL_X
|CLK_70
|}
'''TEXT''': Enable text layer

'''OVRLY''': Overlay text on graphics, by making text background transparent. See '''FON_OVLY'''

'''GRAPH''': Enable graphics layers (tile, sprites, bitmaps)

'''BITMAP''': Enable bitmap layers (if '''GRAPH''' is also set)

'''TILE''': Enable tile layers (if '''GRAPH''' is also set)

'''SPRITE''': Enable sprite layers (if '''GRAPH''' is also set)

'''GAMMA''': Enable gamma correction

'''CLK_70''': Enable 400p70, else 480p60

'''DBL_X''', '''DBL_Y''': Double text mode character width & height

'''MON_SLP''': Turn off monitor SYNC, putting it into sleep mode

'''FON_OVLY''': Only BG color 0 is transparent in '''OVRLY''' mode. Else, all BG colors are transparent.

'''FON_SET''': Chooses font set 0 or 1

====== $D002: Layers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D002
|$F0:1002
|RW
|
|—
| colspan="3" |Layer 1
|—
| colspan="3" |Layer 0
|-
|$D003
|$F0:1003
|RW
|
|—
|—
|—
|—
|—
| colspan="3" |Layer 2
|-
|
|
|
|Values
| colspan="8" |0-2: Bitmap 0-2
4-6: Tilemap 0-2
|}

====== $D004: Border ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D004
|$F0:1004
|RW
|BRDR_CTRL
|—
| colspan="3" |SCROLL_X
|—
|—
|—
|ENABLE
|-
|$D005
|$F0:1005
|RW
|BRDR_BLUE
| colspan="8" |Border color Blue component
|-
|$D006
|$F0:1006
|RW
|BRDR_GREEN
| colspan="8" |Border color Green component
|-
|$D007
|$F0:1007
|RW
|BRDR_RED
| colspan="8" |Border color Red component
|-
|$D008
|$F0:1008
|RW
|BRDR_WIDTH
|—
|—
|—
| colspan="5" |SIZE_X
|-
|$D009
|$F0:1009
|RW
|BRDR_HEIGHT
|—
|—
|—
| colspan="5" |SIZE_Y
|}

====== $D00D: Background ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D00D
|$F0:100D
|RW
|BGND_BLUE
| colspan="8" |Background color Blue component
|-
|$D00E
|$F0:100E
|RW
|BGND_GREEN
| colspan="8" |Background color Green component
|-
|$D00F
|$F0:100F
|RW
|BGND_RED
| colspan="8" |Background color Red component
|}

====== $D010: Text Cursor ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D010
|$F0:1010
|RW
|CCR
|—
|—
|—
|—
|FLASH_DIS
| colspan="2" |RATE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|$D012
|$F0:1012
|RW
|CCH
| colspan="8" |Cursor character code
|-
|$D014
|$F0:1014
|RW
|CURX
| colspan="8" |Cursor X position (16-bit)
|-
|$D016
|$F0:1016
|RW
|CURY
| colspan="8" |Cursor Y position (16-bit)
|}

====== $D018: Raster ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D018
|$F0:1018
|R
|RAST_COL
| colspan="8" |Raster current column (12-bit)
|-
|$D01A
|$F0:101A
|R
|RAST_ROW
| colspan="8" |Raster current row (12-bit)
|-
|$D018
|$F0:1018
|W
|LINT_CTRL
|—
|—
|—
|—
|—
|—
|—
|ENABLE
|-
|$D019
|$F0:1019
|W
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
|}

===== $D100: Bitmaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D100
|$F0:1100
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
| colspan="8" |Bitmap 2
|-
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
|ENABLE
|-
|
| +1
|RW
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}

===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D200
|$F0:1200
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
| +$00
|W
|
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|-
|
| +$01
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|
| +$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
| +$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
| +$08
|W
|
| colspan="4" |X[3:0]
| colspan="4" |SSX
|-
|
| +$09
|W
|
|—
|—
| colspan="6" |X[9:4]
|-
|
| +$0A
|W
|
| colspan="4" |Y[3:0]
| colspan="4" |SSY
|-
|
| +$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Y[7:4]
|}
'''**''' = For 8×8px tilesets, the first map entry (2 bytes) seems to be skipped, so the pointer needs to point 2 bytes before the actual upper-left starting entry.

For 16×16px tilesets, the tile map pointer directly points to the first entry. Very old cores might have had the same offset required.
{| class="wikitable"
|+Tile Map Entry
!Offset
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +0
| colspan="8" |Tile number
|-
| +1
|—
|—
|—
| colspan="2" |CLUT
| colspan="3" |Tileset
|}

====== $D280: Tilesets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D280
|$F0:1280
|
|
| colspan="8" |Tileset 0
|-
|$D284
|$F0:1284
|
|
| colspan="8" |Tileset 1
|-
|$D288
|$F0:1288
|
|
| colspan="8" |Tileset 2
|-
|$D28C
|$F0:128C
|
|
| colspan="8" |Tileset 3
|-
|$D290
|$F0:1290
|
|
| colspan="8" |Tileset 4
|-
|$D294
|$F0:1294
|
|
| colspan="8" |Tileset 5
|-
|$D298
|$F0:1298
|
|
| colspan="8" |Tileset 6
|-
|$D29C
|$F0:129C
|
|
| colspan="8" |Tileset 7
|-
|
| +0
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|
| +3
|W
|
|—
|—
|—
|—
|SQUARE
|—
|—
|—
|}
{| class="wikitable"
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}

===== $D400: Sound =====

====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D400
|$F0:1400
|
|
| colspan="8" |Left SID
|-
|$D500
|$F0:1500
|
|
| colspan="8" |Right SID
|-
|
| +$00
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
|
| +$02
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$04
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$05
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$06
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$07
|W
|Voice 2
| colspan="8" |Frequency (16-bit)
|-
|
| +$09
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$0B
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$0C
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$0D
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$0E
|W
|Voice 3
| colspan="8" |Frequency (16-bit)
|-
|
| +$10
|W
|
| colspan="8" |Pulse width (12-bit)
|-
|
| +$12
|W
|
|NOISE
|PULSE
|SAW
|TRI
|TEST
|RING
|SYNC
|GATE
|-
|
| +$13
|W
|
| colspan="4" |ATTACK
| colspan="4" |DELAY
|-
|
| +$14
|W
|
| colspan="4" |SUSTAIN
| colspan="4" |RELEASE
|-
|
| +$15
|W
|Misc
|—
|—
|—
|—
|—
| colspan="3" |FC[2:0]
|-
|
| +$16
|W
|
| colspan="8" |FC[10:3]
|-
|
| +$17
|W
|
| colspan="4" |RESONANCE
|EXT
|FILTV3
|FILTV2
|FILTV1
|-
|
| +$18
|W
|
|MUTEV3
|HIGH
|BAND
|LOW
| colspan="4" |VOLUME
|}

====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D580
|$F0:1580
|W
|
| colspan="8" |Address registers for ports $000 - $0FF
|-
|$D581
|$F0:1581
|W
|
| colspan="8" |Data registers for all ports
|-
|$D582
|$F0:1582
|W
|
| colspan="8" |Address register for ports $100 - $1FF
|}

====== $D600: PSGs ======
Main page: [[Use the PSG]]

Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D600
|$F0:1600
|
|
| colspan="8" |PSG Left
|-
|$D608
|$F0:1608
|
|
| colspan="8" |PSG Left + Right
|-
|$D610
|$F0:1610
|
|
| colspan="8" |PSG Right
|}

====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D620
|$F0:1620
|W
|
| colspan="8" |DATA[7:0]
|-
|$D621
|$F0:1621
|W
|
| colspan="7" |REGISTER
|DATA[8]
|-
|$D622
|$F0:1622
|R
|
|—
|—
|—
|—
|—
|—
|—
|BUSY
|-
|
|
|W
|
|—
|—
|—
|—
|—
|—
|—
|START
|}

===== $D630: System =====

====== $D630: UART ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|
|
|
| colspan="9" |'''DLAB = 0'''
|-
|$D630
|$F0:1630
|R
|RXD
| colspan="8" |RX_DATA
|-
|
|
|W
|TXR
| colspan="8" |TX_DATA
|-
|$D631
|$F0:1631
|RW
|IER
|—
|—
|—
|—
|STAT
|ERR
|TXE
|RXA
|-
|
|
|
| colspan="9" |'''DLAB = 1'''
|-
|$D630
|$F0:1630
|RW
|DL
| colspan="8" |DIV (16-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$D632
|$F0:1632
|R
|IIR
| colspan="2" |FIFO
|FIFO64
|—
| colspan="3" |STATE
|/PENDING
|-
|
|
|W
|FCR
| colspan="2" |RXT
|FIFO64
|—
|DMA
|TXR
|RXR
|FIFOE
|-
|$D633
|$F0:1633
|RW
|LCR
|DLAB
|—
| colspan="3" |PARITY
|STOP
| colspan="2" |DATA
|}

====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D640
|$F0:1640
|RW
|PS2_CTRL
|—
|—
|MCLR
|KCLR
|M_WR
|—
|K_WR
|—
|-
|$D641
|$F0:1641
|RW
|PS2_OUT
| colspan="8" |Data to keyboard
|-
|$D642
|$F0:1642
|R
|KBD_IN
| colspan="8" |Data in from keyboard FIFO
|-
|$D643
|$F0:1643
|R
|MS_IN
| colspan="8" |Data in from mouse FIFO
|-
|$D644
|$F0:1644
|R
|PS2_STAT
|K_AK
|K_NK
|M_AK
|M_NK
|—
|—
|MEMP
|KEMP
|}

====== $D650: Timers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D650
|$F0:1650
|W
|T0_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T0_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D651
|$F0:1651
|RW
|T0_VAL
| colspan="8" |VAL (24-bit)
|-
|$D654
|$F0:1654
|RW
|T0_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D655
|$F0:1655
|RW
|T0_CMP
| colspan="8" |CMP (24-bit)
|-
|
|
|
|
|
|
|
|
|
|
|
|
|-
|$D658
|$F0:1658
|W
|T1_CTR
|—
|—
|—
|—
|UP
|LD
|CLR
|EN
|-
|
|
|R
|T1_STAT
|—
|—
|—
|—
|—
|—
|—
|EQ
|-
|$D659
|$F0:1659
|RW
|T1_VAL
| colspan="8" |VAL (24-bit)
|-
|$D65C
|$F0:165C
|RW
|T1_CMP_CTR
|—
|—
|—
|—
|—
|—
|RELD
|RECLR
|-
|$D65D
|$F0:165D
|RW
|T1_CMP
| colspan="8" |CMP (24-bit)
|}

====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D660
|$F0:1660
|
|INT_PENDING
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D664
|$F0:1664
|
|INT_POLARITY
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D668
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|$D66C
|$F0:166C
|
|INT_MASK
| colspan="8" |Per-interrupt flags (24-bit)
|-
|
| +0 & $01
|
|INT_VKY_SOF
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
|-
|
| +0 & $02
|
|INT_VKY_SOL
| colspan="8" |Start of Line interrupt
|-
|
| +0 & $04
|
|INT_PS2_KBD
| colspan="8" |PS/2 keyboard event
|-
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|
| +0 & $10
|
|INT_TIMER_0
| colspan="8" |TIMER0 has reached its target value
|-
|
| +0 & $20
|
|INT_TIMER_1
| colspan="8" |TIMER1 has reached its target value
|-
|
| +0 & $80
|
|INT_CARTRIDGE
| colspan="8" |Interrupt asserted from cartridge port
|-
|
|
|
|
| colspan="8" |
|-
|
| +1 & $01
|
|INT_UART
| colspan="8" |The UART is ready to receive or send data
|-
|
| +1 & $10
|
|INT_RTC
| colspan="8" |Interrupt from real time clock chip
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|
| +1 & $40
|
|INT_VIA1
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|-
|
| +1 & $80
|
|INT_SDC_INS
| colspan="8" |SD Card has been inserted
|-
|
|
|
|
| colspan="8" |
|-
|
| +2 & $01
|
|IEC_DATA_i
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|
| +2 & $08
|
|IEC_SREQ_i
| colspan="8" |IEC service request in
|}

====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D670
|$F0:1670
|R
|
|GAMMA
|USER2
|USER1
|USER0
| colspan="4" |BOOT
|}

====== $D680: IEC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D680
|$F0:1680
|R
|IEC_I
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|$D681
|$F0:1681
|RW
|IEC_O
|SRQ_o
|RST_o
|NMI_EN
|ATN_o
|—
|—
|CLK_o
|DAT_o
|}

====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D690
|$F0:1690
|RW
|Seconds
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D691
|$F0:1691
|RW
|Seconds Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D692
|$F0:1692
|RW
|Minutes
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D693
|$F0:1693
|RW
|Minutes Alarm
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|$D694
|$F0:1694
|RW
|Hours
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D695
|$F0:1695
|RW
|Hours Alarm
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D696
|$F0:1696
|RW
|Days
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D697
|$F0:1697
|RW
|Days Alarm
|0
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|$D698
|$F0:1698
|RW
|Day of Week
|0
|0
|0
|0
|0
| colspan="3" |1s digit
|-
|$D699
|$F0:1699
|RW
|Month
|0
|0
|0
|10s digit
| colspan="4" |1s digit
|-
|$D69A
|$F0:169A
|RW
|Year
| colspan="4" |10s digit
| colspan="4" |1s digit
|-
|$D69B
|$F0:169B
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}

====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

====== $D6A7: F256k Series LEDs ======
'''NOTE:''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}

====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}

====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}

====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}

===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].

===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}

===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]

Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}

===== $D900: Sprites =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24

2: 16×16

3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}

===== $DB00: Moar system =====

====== $DB00: VIAs ======
See: [[Keyboard raw codes]]

<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}

====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.

====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}

===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}

===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}

===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

== IO Page 1 ==

====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|RW
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|RW
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|}
== IO Page 2 ==

====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $DFFF
|$F0:4000 - $F0:5FFF
|RW
|
|Text screen character matrix
|}
1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}

== IO Page 3 ==

====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$C000 - $DFFF
|$F0:6000 - $F0:7FFF
|RW
|
| colspan="8" |Text screen color matrix
|-
|
|
|
|
| colspan="4" |FG color (0-15)
| colspan="4" |BG color (0-15)
|}
Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

WF FPGA Ideas

2026-02-18T01:19:45Z

WF:

== Video enhancements ==
[[WF16 Video Architecture]]

== Math coprocessor ==
[[FPU Accumulator]]

== SDCard ==
Auto-tx on read. Could supersede this with auto-reading a 16-bit length to a storage pointer, running in the background, flag or interrupt when done. Loading straight into DDR3 would be good once audio/video can read from there.

Stream MP3 or MIDI file from disk (or ddr3?) straight to chips

== Bootstrap and Machine Identity ==
Access to the cores SDCard. Name something better than the current hardcoded names.

Soft-boot into one of the other cores, instead of relying on jumpers to select the core. Have an extended PGZ header or new file format that can request such things. Note that PGZ should say how many and which 8k blocks or 64k banks it's hardcoded for. Should be another load format for "play nice" system tools that can be simultaneously loaded.

Identify cores by an 8 character ASCII string, instead of bit fields. Maybe have a version number (16 bit) per release of any named platform.

Have different ROM loads for different cores? Or boot from RAM if some magic bytes occur there instead of ROM., though that would be part of the ROM boot that can do that, what ISA would the code be?

RP2040 uses the Slave SelectMAX x8 config interface of the FPGA, and its 8 data pins should be GPIO for the FPGA to talk back to the RP after it's up and running (unless the pins are used for something else). The RP software needs updating for that.

Simplest comms would be splitting the 8-bit path into two 4-bit independent directional channels. Clock (toggle when new data is sent), Ack (receiver toggles when it's read), 2 data bits. All polled on the software end. The RP2040 could be crunching FAT32 stuff while the FPGA is waiting to write to it, no problem.

SRAM can be retained between resets:

<code>char my_crash_info[100] __attribute__((section(".uninitialized_data")));</code>

and with a macro:

<code>#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group</code>

<code>datetime_t __uninitialized_ram(persist_date);</code>

=== Tentatively Proposed RP2040 Startup ===

* Read SD Card for magic <code>/MYCORE.TXT</code> file containing the full path of the core filename to boot.
** If this exists, DIP switches can be some form of override. Need to be able to break in if something messes up. On configuring MYCORE, always tell the user to set their DIP switches to 00.
** If this doesn't exist, oldsk00l DIP switches determine the core to boot.
* Load compressed core file from card and get the FPGA going.
** Set the FPGA comm handshake pins to 0 before releasing the init/reset command to the FPGA.
* Load <code>/RPLIB</code> library and jump into it, if exists (else infinite loop). This runs whatever library functionality can talk to the FPGA, and is upgradable as a file through the loaded utilities.
The library should have functions to browse the cores sdcard, and select which file to boot with.

TODO - do the core selection DIP pins also hit the FPGA for flash banking? If so, then we might not be able to escape them.

== Timers ==
Ensure that the 24-bit value latches when the LSB is read (or the MSB is written?) for consistent reads.

== Wavetable Audio ==
Some form of wavetable audio is sorely missing for Amiga, TG16, SNES, Soundblaster era audio, especially sound effects. Basic multiple channels of stereo or panned mono, uncompressed samples, support some simple compression formats.

Pull small buffers of audio into the FPGA from RAM, keep 2 live at a time, one playing, one buffered. At 25MHz with a 48KHz sample rate, 1 sample lasts 520 cycles (20µsec), could be fast enough to fetch while the last sample is playing and just single-buffer it? Or even a rolling window Should also support just-in-time software generation of each buffer, with IRQ notifications.

Stretch samples to whatever the output sampling rate is. Linear interpolation would be neat, but probably optional. Same with the decay-to-zero that many old synth chips had.

== Sound Chip Instances ==
Instead of duplicating hardware instances of sound chips, multiplex all their registers and internal variables. Access would select 1 of them, and the hardware would run with that multiplexer active on all its values. Compare the size taken, depends on how complex the chip is.

Since sound chips don't need to be that fast, serially looping through and executing a cycle, accumulating their output, for the final audio sample would be fine. Some of them do this internally with their voices anyway.

Register to select which instance(s) to use, so programs can be agnostic to what sound context exists with other things. Probably expose 2 chips at a time through the IO registers, with a separate one to select which bank of 2 to use. At least for mono chips, or those which are commonly in pairs. Stereo chips could just have 1 register set exposed.

== 65816 support ==
Remap page 0 into any 64kB bank, allowing direct page, stack, etc, to have its own swappable space. However, need to consider how this goes for interrupts. An interrupt will probably have to remap to hardware bank 0, but then somehow restore the bank that used to be there. Keeping the upper 256 bytes locked somewhere (flash or bank 0 RAM) would solve that. The 8kB MMU can be used for these purposes already, but I wonder if the full bank swapping might be easier, but likely not really necessary as long as the MMU is around.

== FPGA-based CPU ==
65816 but with a genuine 16-bit data bus.

Keep 6809 in the same core with the 65816 running. Switch between either at any time (bus master), or alternate cycles. At core2x speed, they could each run at 6MHz alternately hitting the SRAM.

If the bus can be more dynamic, especially during vblank/hblank, the CPUs can run a lot faster there.

== Bitstream readers/writers ==
Write a byte or word to a FPGA location, it takes a CPU cycle to write it, and bumps its pointer.

For a bit stream, a 32-bit bitpointer covers 4Gb = 512MB. A write would need to know the width to write. Maybe 16 registers, write a value to one of those to declare how many bits from the written value to write. This actually allows the index register to determine width dynamically, which is nice. Both read & write interfaces should use this. A complete hack but easier to use would be to have 18 regs. For any width >8 bits, a 2nd access to the next register would grab the high byte, even though it's technically the trigger for the next higher. But this would get confusing in 65816 16-bit mode, accessing lower lengths.

Separate read & write context, so copies, decompression, etc, can be done. Bit pointers can be directly read/written as well. Direction is always in the positive direction, though, at least for now.

Probably good to support 0-length, for dynamically computed lengths. So with 0-16 supported, that's 17 entry points, kinda messy.

Also, skip forward N bits without a read or write. Technically this could just be a read N bits and ignore the value, but this should be 0-65535 bits skipped. Could also just do a 32-bit add on the pointer register.

8bit interface: 2 bitpointers, then 8 byte locs for pointer 0, and 8 byte locs for pointer 1.

16bit interface: 2 bitpointers, then 16 word locs for pointer 0, 16 word locs for pointer 1. Writes triggered on high byte write. Reads trigger on low byte read, which readies the high byte.

This is a CPU-blocking interface for reads, buffered for writes.

== Optical Keyboard ==
Can this be sent as 9 events of 8bits, instead of 8 events of 9 bits (2 bytes)? However the self-describing row number might be useful to keep.

== RLE Format(s) ==
RLE layers, DMA, and potentially sprites can use RLE encoding.
{| class="wikitable"
|+Span-based RLE formats
!bpp
!Layout
!length
!Max compression
!Breakeven
|-
|1
|<code>clllllll</code>
|1-128
|16:1 byte
|8px
|-
|2
|<code>cc111111</code>
|1-64
|16:1 byte
|4 pixels
|-
|4
|<code>ccccllll</code>
|1-16
|4:1 byte
|2 pixels
|-
|4
|<code>ccccCCCC llllllll llllllll</code>
|1-256
|170:1 byte (512:3)
|3+3 pixels
|-
|8
|<code>cccccccc llllllll</code>
|1-256
|128:1 byte
|2 pixels
|}
However, it would be useful to have spans of literal pixels as well, instead of just solid color span fills.

<code>0lllllll cccccccc</code> = span length L of color C, 0 = transparent

<code>1lllllll cccccccc...</code>= L count of individual pixels

For a bpp less than 8, probably require them to fill an even byte or word count

For now, RLE layers should be simple length + 8bpp aligned words. RLE bitmaps would be something different, maybe it's too flexible so we should just leave that to the CPU. It would save a lot of bandwidth for bitmap overlay layers with large transparent windows, though.

== DMA/Blitter ==
Maybe separate out 2d mode into its own blitter?

Flag to mask out the 'fill/mask' color (default 0)

Clip to output screen dimensions.

Xflip, yflip, maybe 90° rotation, but that means dest dimensions change? Scaling? Full affine transform?

Unpack RLE graphics, for better memory usage. Could still do x/y flip because this isn't raster-dependent. Must know the total x/y though if clipping is supported

Fields:

* bpp (could expand from src to dest given an offset?)
* src w/h/stride
* dest w/h/stride

'''TODO - V2'''

Clipping? Or should the src/dest be handled in software?

Ideally, there'd be a clip bounds defined at the dest address, w, h, stride, bpp. The source address is defined, and it's blitted into an x/y in the dest screen, automatically clipped. This could also be used as a pixel/stamp plotter.

If there end up being a large number of parameters for a src or dest, it would be nice to have multiple profiles. Either read src/dest profiles from ram, or have say 4 src & 4 dests saved, and blit from src N to dest M.

RLE graphics should probably save their w/h and mode implicitly as the first 2 words, as they are their own free-form shapes.

Since DMA currently only takes place during VBLANK, could be more efficient to have a DMA list to run when VSYNC hits, blasting those out as fast as possible.

For 1bpp (or maybe others, too?) and/or/nor/nand/xor modes would be necessary.

WF16 Video Architecture

2026-02-18T01:16:19Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.
{| class="wikitable"
|+Per Line Sprite Limits
!
!Sprites
!Pixels
!
|-
|'''SNES'''
|32
|34*8 = 272
|
|-
|'''Genesis'''
|20
|20*16 = 320
|
|-
|'''TG16'''
|16 single-wide
|256
|
|-
|'''F256K'''
|64 or 128 (no limit)
|
|
|-
|'''CX16'''
|6-57
|≤512
|[https://cx16forum.com/forum/viewtopic.php?p=26089#p26089]
|-
|'''Neo Geo'''
|96
|1536
|
|-
|'''Commando'''
|?
|
|
|-
|'''CPS-1'''
| colspan="3" |none, sprite frame buffer
|}
'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-02-17T22:19:54Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop. Probably have an 8-bit register access mode (high bytes & low bytes in different areas, for 256 sprites) vs 16-bit register access mode (for 65816 16-bit copies with indices from 0-510).

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-02-17T00:36:32Z

WF: /* Sprites */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

Need to ensure that tile layers are max 65536 pixels wide/tall, since that's what the scroll layers deal with.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

I do like the genesis idea of having a linked list of active sprites, as it can save time scanning the active sprites and finishing early. Question is should there be multiple sprite layers, each with their own list head, or one sprite list with each sprite having its depth independently set with its priority bits?

For transparency, we probably need 2 sprite linebuffers, one for the transparent part, and one for the solid part. Each holds its own layer in the upper bits. 18 bit entries = 16-bit 4444 RGBA, plus 2 bits layer selection. Now, there's nothing for enabling/disabling the pixel, though. The transparency layer could be enabled by alpha channel, and because of stacked blending of transparent requires the actual full color value. The solid layer could do clut + 8bpp + enable bit, for 13 bits total, or 12bpp plus 2bpp layer plus 1bbp enable, for 15 bits total, since we know that's not transparent. We probably want a flag for the layer/global as to whether sprite transparency stacks or not, since enabling it will blend deeper transparent sprite pixels from being obscured to the topmost transparency layer.

Sprite register should probably be a structure of arrays, so you can wholesale copy x/y locations faster than copying literally the entire sprite definition block every frame. Individual sprite updates for color, frame, etc can be set during animation handling, and directly set the sprite register instead of that needing to be part of the update loop.

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Length is 1-128, there is no zero-length span.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon filling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?

WF16 Video Architecture

2026-02-16T23:24:28Z

WF: /* Layers */

== Global settings ==
CRT emulation, only for low resolution layers.

640×480 for 4:3 output, or 960×540 for 16:9 output, if bandwidth can run it. Requires 1.6875× the bandwidth.

Non-integer pixel aspect flags, again only for low res layers. Match 320×200 and 256×200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz

Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extending vblank time and keeping pixel clock the same. If 640×400 res is still used, have it at 60Hz, again same pixel clock but longer vblank.

Global scroll register, for setting where 0,0 is on the display. This might also change how the raster lines are counted, going from say -100 to 380 instead of 0 to 480, to line up with borders and such.

Let the mouse pointer pick a CLUT, instead of being locked to grayscale. Or have its own dedicated 16-color one.

== Palettes ==
Reduce from 24-bit to 16-bit, better suited to 65816, and makes a lot of addressing simpler.

5-5-5-1 masked, or 4-4-4-4 RGBA? Leaning towards the latter. Using transparency 0=opaque, 15=fully transparent is probably easier.

Have a FPGA block which separates & combines 4 values into 1, all R/W registers, avoid all the shifting. Include signed clamping when converting to the single RGB word.

'''Rougher ideas'''

Palettes are always 4-4-4-4, but direct color 5-5-5-1 or 4-4-4-4 can be used for bitmap layers? Probably best to keep it the same, but given clear displays today, the 5-5-5 would look better for full-color backgrounds.

{| class="wikitable"
|+4bpp Palette Configurations
!
!Entries
!Depth
!Palettes
!Tiles
!Sprites
!Notes
|-
|'''SNES'''
|256
|555
|16×16
|0-7
|8-15
|
|-
|'''Genesis'''
|64
|333
|4×16
|0-3
|0-3
|
|-
|'''TG16'''
|512
|333
|32×16
|0-15
|16-31
|
|-
|'''CX16'''
|256
|444
|16×16
|0-15
|0-15
|
|-
|'''Neo Geo'''
|4096
|444
|256×16
|—
|0-255
|Everything is sprites
|-
|'''Commando'''
|256
|444
|16×16
|0-7
|8-15
|
|-
|'''CPS-1'''
|3072
|4444
|192×16
|0-31 + layer
|0-31
|4bit brightness, each layer/type has its own 32 palettes
|}
== HDMA ==
After a line has been rendered to the line buffer, run the HDMA list. If the HDMA list is done, then trigger the EOL interrupt if enabled. The timing that a line & HDMA takes is dynamic. The EOL should always be fired for a line even if there is no time left.

Ideally, if the NMI line could be connected, the EOL interrupt can be dedicated there for minimizing latency.

At first, the HDMA list should contain a line number to wait for, a count, and number of address/data pairs in video IO space to write, and whether to fire an interrupt.

Advanced features would be to load a value from a table, offset by the raster number. And run the HDMA (with optional interrupt) every line until the target line is reached.

There could be some BRAM dedicated to HDMA use or other on-chip variable storage. Would free up the bus, and take smaller indexing for where to copy from. Also, could set some state vars.

The rasterline would likely be the graphics line, not the hi-res line but this could also be an option.

The HDMA "program counter" is visible and editable, and can be safely modified after EOL interrupt. If it's $000000, then it's disabled? Should HDMA lists be on-chip? Have HDMA variables on-chip, referred to by the copies by small index?

This has the effect of externalizing and obsoleting the rasterline interrupt registers, as the HDMA could just fire them on a list of lines instead, without running any actual DMA.

SNES sets up the destination as part of the HDMA config, then each line only has the data to write. Saves cycles, and is probably reasonable to implement, given what these tend to be used for. Examples at https://snes.nesdev.org/wiki/HDMA_examples

While it might be a lot for HDMA, DMA'ing in a chunk of sprite registers from SRAM would be nice. This might be something for normal DMA during VBLANK.

== Line Buffers ==
Use 36bit BRAMs, storing 3 12-bit pixels per word. This is the final output buffer, no alpha necessary.

2 line buffers would be used for CRT emulations, or 3 if we need a work one. 320px wide / 3 = 107 words per line, 321 words total (3 linebuffers), 11,556 bits.

== Layers ==
Every layer def has these:

* Type (tile, bitmap, RLE, sprite?)
* Base pointer (could be page-aligned 16-bit, for 16MB range?, else 32-bit pointer)
* x/y pixel scroll (16-bit wrapping). Could share these in scroll groups, but not a big deal to duplicate these. This includes scrolling sprite layers
* CLUT selection
* Bit depth?
* Clip window?
* Masking enable & layer target
* Last layer flag? Meaning color 0 isn't transparent and uses the CLUT color to fill in the background
* High or low resolution? Some modes and bit depths are low enough bandwidth to do at 480p

64-byte cache per layer, for retaining sprite/tile graphics for reuse (more if bpp is smaller), or a readahead buffer for DDR3 for RLE and bitmap modes, which don't reuse anything anyway

=== No-overdraw bandwidth reduction ===
Have multiple hardware instances of layer renderers, all fighting for external bandwidth. Render front-to-back, with transparent pixels causing the next layer underneath to want to draw that pixel. Each layer only requests individual pixels that it needs to draw, and keeps some cache for redrawing the same sprite/tile on the same line. The first layer gets all pixels requested. The only wasted reads are when a read pixel is transparent and dispatches deeper, and 16-bit wide reads where not all the bits are used.

Tilemap data is probably fetched regardless if it's in DDR3. For SRAM, just grabbing & caching the current tile is fine. Tile 0 assumed blank means avoiding fetching any of those pixels.

=== Alpha Transparency ===
A pixel entry in the line buffer contains a 12-bit ARGB value, and goes through potentially 3 states: Uninitialized, holding transparent, opaque, with holding transparent being optional.
{| class="wikitable"
|+Action→Next State
!Init State
!Empty Pixel
!Transparent Pixel
!Opaque Pixel
|-
|Uninit
|No-op → Uninit
|Set → Transparent
|Set → Opaque
|-
|Transparent
|No-op → Transparent
|Blend (or no-op) → Transparent
|Blend → Opaque
|}
When transitioning to opaque, the pixel is complete. The common case is uninit to opaque, and shouldn't be done with extra clock cycles, unless the blend is constant and pipelined.

For simplicity, the 'alpha' is actually a transparency channel, with 0 = opaque, and 15 = fully transparent. A layer can override transparency, or any individual palette entry can have non-zero transparency. For most cases, a pixel index value of 0 is a skipped pixel and the equivalent of $F000 (fully transparent black).

Individual layers, sprites, can have a transparency override, ignoring the palette alpha value. If they don't, transparency from the palette per color can still be obeyed. Maybe palette transparency needs to be enabled as well, just using the 12-bit color by default, meaning we can still use 0→f as clear→opaque as standard.

=== Masking Layers ===
Any layer can be used as a mask, to clip out layers underneath it. Wherever a solid pixel would be drawn, this would cause the pixel rendering to skip down to a layer lower in the stack. RLE layers would probably be the best for this, but any layer can be used this way to stencil out graphics. Instead of just masking out the immediate layer below it, it can choose which layer to skip to, so it can mask out an entire consecutive stack of layers.

'''TODO'''

Buffering alpha sprites with no-overdraw is harder, probably needs its own linebuffer. Both the alpha and opaque layers need to track their own layer depth per pixel when merging together, as maybe only the alpha is visible but not the further back opaque sprite. Simplifications would be that alpha sprites don't show any sprites underneath, only tiles, but that's lame. Another would be that alpha sprites that overlap other sprites always combine with sprites and can't have tiles underneath. That is lame as well. The only real solution is to have the f2b trace through the sprite priority layers instead of having a single combined sprite line buffer, or split out sprite transparency into its own line buffer, with each pixel having its own priority number in both sprite line buffers. Or just support alpha transparency in tile/bitmap/rle layers and not sprites. Again lame, but probably the most workable solution. A small bitmap layer basically acts like a sprite anyway.

Oh, I guess we need an alpha mode as well. Averaging, brightening, dimming, threshold, gel, etc.

== Indexed Bit Depth ==
Currently, everything is 8bpp, which is high bandwidth, more work to create artwork, and doesn't port as easily from other systems that use multiple palette swaps onscreen.

For tiles, sprites, and bitmaps, choose 1/2/4/8 bpp. Direct color 16-bit bitmaps would be separate from paletted bitmaps.

Each layer can select a CLUT. Each sprite or tile points to either a starting palette entry, or maybe a bitmask to OR into it. Pixels that are affected by local color would have those bits be 0, while static colors have those bits all 1. This can drastically reduce the potential colors available, though. If you have 8 shades of the selected color, that means only 32 static colors in the rest. Very wasteful, but functional.

== Bitmaps ==
Option to wrap. Else, it shows blank pixels outside its range. Divmod can be done once per line.

Size x/y pixels

Small bitmaps with wrapping could make for easy wipes and parallax effects, covering the entire screen with a pattern.

During render, recompute the starting address to allow raster effects including Y stretch/squash.

1/2/4/8 bpp for indexed bitmaps, option for 4-4-4-4 or 5-5-5-1 for direct color bitmaps.

DDR3 suits bitmaps the best, ensure that gets supported. A 640×480×8bpp (+307,200 $4B000 bytes) single layer mode would also be nice for GUI and PC game ports, especially with blitter support. Scrolling can still be supported, maybe more than 1 layer might be doable as well.

== Tiles ==
Layer: Base pointer = Tilemap pointer, add tilegfx pointer

Map size x/y tiles

Option to wrap.

By default, tile 0 is assumed empty and no pixels are read, saving bandwidth. Can be used for metadata. Option to have tile 0 non-empty? Maybe it should be tile $ffff (or whatever the max index is, given flip bits?) That would never be in the tileset anyway.

For DDR3 tilemaps, it reads an entire row into a buffer. For SRAM, it fetches each tilemap entry as it becomes visible, then fetches the pixels separately, and caches them.

{| class="wikitable"
|+Tile attributes of various platforms
!
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|VFlip
|HFlip
|Priority
| colspan="3" |Palette (0-7)
| colspan="10" |Tile (0-1023)
|-
|'''Genesis'''
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|'''TG16'''
| colspan="4" |Palette (0-15)
| colspan="12" |Tile (0-4095)
|-
|'''CX16'''
| colspan="4" |Palette (0-15)
|VFlip
|HFlip
| colspan="10" |Tile (0-1023)
|-
|'''Neo Geo attr'''
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|'''Commando'''
| colspan="2" |Tile MSB (0-1023)
|VFlip
|HFlip
| colspan="4" |Palette (0-15)
| colspan="8" |Tile LSB
|-
|'''CPS-1 attr'''
|—
|—
|—
|—
|—
|—
|—
| colspan="2" |Priority
|VFlip
|HFlip
| colspan="5" |Palette (0-31)
|}
Neo Geo and CPS-1 uses 32 bits per tile. 16-bit LSB tile number is excluded, 16-bit attributes (above).

=== Tilegfx ===
These are self-describing, with a header that takes up tile 0's pixel space? Having tile $FFFF be transparent actually would be easier for tileset creation, because that would always exist and take no memory or extra flags.

bpp (1,2,4,8), size (8×8, 16×16 (32×32, 64×64?)), bitmap mode, which would give it a stride of 256 bytes no matter the bpp (or take a stride byte/word value, more complex computation but just once per rasterline).

1bpp tiles are interesting, in that we could have transparency modes like text: fg only (direct color selection?), fg/bg (palette index where the 2 start from), fg/bgp (bg0 is always transparent, rest are solid).

I've never seen a platform with the Foenix's notion of multiple tilesets addressable from a single tilemap. I'm not sure that's really ever used anywhere either. It's interesting, but not sure how useful it would be to keep, vs the >8bit tile indices above. The only time it would be specifically useful if 2 tile layers share same partial tileset, but have additional differences. I don't really see a super pressing need for that. I also think that the size, bpp, etc should be part of the tilemap/layer definition, not separated off into its own table of tilesets.

'''Rougher ideas'''

Neo Geo has auto-animating tiles/sprites. 4 or 8 tiles in a row in the tileset can be cycled through for animation. (cycling through low 2 or 3 bits of tile index). Global or layer-specific config for how may frames per step.

Meta-tilemap mode, so the tilemap holds entries that are 2×2 or 4×4 hardware tilemap entries.

Priorities aren't all that often use, but might be a good feature to have, especially to save on tilemap layers and scads of empty entries in those additional layers. Place the "background" in front of the sprite layer, with the tile either high priority drawing, or deferring to the sprite layer below it. If the priority is low, it passes the color to the sprite layer, and if the sprite layer has no pixel, it draws that bg pixel. If the tile pixel is transparent, then transparent behavior applies regardless of priority and nothing is different.

A CPS-1 style priority bit setting (16-bit, priority per color in that tile) might be interesting, but I'd say a half-and-half mode (lower 8 colors are lower priority, higher 8 colors are higher priority), or higher 4 colors etc, might be more compact and useful. It puts more constraints on the colors, but I would think certain foreground objects might have their own colors anyway?

== Sprites ==
H-flip at the very minimum. If V-flip and 90° (since all sprites/tiles are square sized), then all 8 orientations and flips are possible. Rotation is only available in SRAM.

16-bit sprite image selection from base pointer, based on bpp & size. Flip bits might be at MSBs of the word. 3 flip bits means 8192 sprite images.

Sprite sheet mode (kinda like square for tilesets), with a declared stride.

Color selection, direct for 1bpp, starting palette offset for 2/4bpp. Note that both of these could be expressed by OR'ing a mask on top of the color.

Need to figure out something for 8bpp color, to have palette swaps for limited ranges. The layer could have a color range/mask where all colors less than that use the sprite color. But this can probably be done with just an OR mask (or XOR for fun?). 8bpp sprites would normally have a 0 'color', palette swaps would leave a range of bits open and use the individual sprite color to set that, but we don't want that done on all bits, only those that are in "palette range", hence the layer setting. Maybe also only when the color is nonzero? or non-FF? Or if the color is 0-16, then it has 16 color selections as a 4bpp color? Colors 17-255 would be normal. Use the top bit of the color byte to select this coloring mode.

8×8, 16×16, 32×32, 64×64 sizes (2 bit selection, forget 24×24) TG16 had 64×64 and did interesting pseudo-layer and huge enemy stuff with it.

1,2,4,8 bpp (2 bit selection)

(or should bpp & size be for the layer? might make for simpler implementation, but varying sprite sizes are probably good. Bpp might still be a consideration for layer config

Overdraw avoidance eliminates pulling in unseen pixels, which prevents hardware collision detection, which is fine.

{| class="wikitable"
|+Sprite definitions of various platforms
!
!VRAM
!Num
!Bytes
!15
!14
!13
!12
!11
!10
!9
!8
!7
!6
!5
!4
!3
!2
!1
!0
|-
|'''SNES'''
|64kB
|128
|4¼
| colspan="8" |Y pos (0-255)
| colspan="8" |X Pos (0-255)
|-
|
|
|
|
|VFlip
|HFlip
| colspan="2" |Priority
| colspan="3" |Palette (0-7)
| colspan="9" |Tile (0-511)
|-
|
|
|
|
| colspan="14" |(packed with other sprite x msb & size)
|X Pos MSB
|Size
|-
| colspan="20" |
|-
|'''Genesis'''
|64kB
|80
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) -256
|-
|
|
|
|
|—
|—
|—
|—
| colspan="2" |Width (1-4)×8
| colspan="2" |Height (1-4)×8
|—
| colspan="7" |Link (next sprite in draw order)
|-
|
|
|
|
|Priority
| colspan="2" |Palette (0-3)
|VFlip
|HFlip
| colspan="11" |Tile (0-2047)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
|—
| colspan="9" |X Pos (0-511) -128
|-
| colspan="20" |
|-
|'''TG16'''
|64kB
|64
|8
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-1023) relative
|-
|
|
|
|
|—
|—
|—
|—
|—
| colspan="11" |Tile (0-2047), address = tile×32 regardless of sprite size
|-
|
|
|
|
|VFlip
|—
| colspan="2" |Height (16,32,64)
|HFlip
|—
|—
|Width (16,32)
|Priority
|—
|—
|—
| colspan="4" |Palette (0-15)
|-
| colspan="20" |
|-
|'''F256K'''
|2MB
|64
|6
| colspan="8" |Tile Address MSB
|—
| colspan="2" |Size
| colspan="2" |Priority
| colspan="2" |Palette (0-3)
|Enable
|-
|
|
|
|
| colspan="16" |Tile Address LSB
|-
|
|
|
|
| colspan="16" |X Pos (0-65535)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535)
|-
| colspan="20" |
|-
|'''CX16'''
|128kB
|128
|8
|8bpp
|—
|—
| colspan="13" |Tile (0-4095), address = tile×32 regardless of sprite size
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |X Pos (0-511)
|-
|
|
|
|
|—
|—
|—
|—
|—
|—
| colspan="10" |Y Pos (0-511)
|-
|
|
|
|
| colspan="2" |Height (8,16,32,64)
| colspan="2" |Width (8,16,32,64)
| colspan="4" |Palette (0-15)
| colspan="4" |Collision mask
| colspan="2" |Priority
|VFlip
|HFlip
|-
| colspan="20" |
|-
|'''Neo Geo'''
|ROM
|380
|134
| colspan="16" |Tile LSB
|-
|
|
|
|
| colspan="8" |Palette (0-255)
| colspan="4" |Tile MSB (0-1,048,575)
|Auto-anim 3b
|Auto-anim 2b
|VFlip
|HFlip
|-
|
|
|
|
|—
|—
|—
|—
| colspan="4" |HShrink (15-0)
| colspan="8" |VShrink (255-0)
|-
|
|
|
|
| colspan="9" |Y Pos (0-511)
|Sticky
| colspan="6" |Height in tiles (0-32, 33 = special wrap mode)
|-
|
|
|
|
| colspan="9" |X Pos (0-511)
|—
|—
|—
|—
|—
|—
|—
|-
| colspan="20" |
|-
|'''Commando'''
|ROM
|128
|4
| colspan="3" |Tile MSB (0-2047)
|X Pos MSB
|HFlip
| colspan="3" |Palette (0-7)
| colspan="8" |Tile LSB
|-
|
|
|
|
| colspan="8" |X Pos (0-255)
| colspan="8" |Y Pos (0-255)
|-
| colspan="20" |
|-
|'''CPS-1'''
|ROM
|256
|8
| colspan="16" |X Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Y Pos (0-65535?)
|-
|
|
|
|
| colspan="16" |Tile (0-65535)
|-
|
|
|
|
| colspan="4" |Height (in sprites)
| colspan="4" |Width (in sprites)
|—
|YFlip
|XFlip
| colspan="5" |Palette (0-31)
|}
SNES has 2 sprite sizes globally selectable, and the per-sprite bit sets which to use.

One Neo Geo sprite is a tower of up to 32 tiles (first 2 words above), which makes the attribute size that large: 2 words × 32 tiles, plus 3 other attribute/position words. The sticky bit is to place the next sprite immediately to the right of the current one.

"ROM is listed for "VRAM" when there's no RAM for pixel data, and that's stored in ROM. VRAM tends to describe register tables and the char matrix in these platforms.

CPS-1 sprite tiles are all 16x16 pixels.

'''Rougher ideas'''

Are all sprites independently defined and layered? Are they all from the same base pointer? Would need multiple layer definitions to give multiple base pointers, and that might be a good idea? Each layer involved could take 64 sprites out of 256, max 4 sprite "layers". Maybe that's not something that should be layer-based, but global to the sprite system. 4 base pointers, 4 groups of 64 sprites, 4 hardware elements scanning the sprite registers in parallel.

Unlimited height sprites? fixed width

8bpp color register could be used to bank a subset of colors, maybe a color range (0-7) can be cycled while others are fixed. Think of Age of Empires 1 recoloring for instance. Or just use that to select a CLUT, overriding the layer's selection.

Select the color to be transparent? If using a fixed smaller palette, like DB16/32, then each sprite could pick a different one. Pico-8 has a 16-bit mask for which colors to include or not, which is interesting.

Cut-out sprites wouldn't display, but would clear any pixel from sprites above it, allowing sprites below to show through. Or, it could skip the sprite immediately below if it has a pixel, masking a single sprite, which might be easier to implement.

Figure out sprite zooming. No rotation,just scaling, not inverting with this? Can grow or shrink independently in x & y. Maybe bresenham? Probably want sub-pixel accuracy, 16-bit with fixed point? Or full 32-bit fixed? x1/x2/y1/y2 dest rectangle maybe?

== RLE ==
Layer has a height (width is undefined).

The base pointer points to an array of <code>height</code>× 16-bit offsets, one for each line, indexed from the base pointer. Each line is an non-demarcated concatenation of tags:

<code>0lllllll cccccccc</code>length + color pair, color 0 is typically transparent

<code>1lllllll c...</code>length + literal pixels.

Uses:

* Wipes
* Solid color borders
* Raster bars without interrupts
* SNES-style explosion or light ray effects (esp with transparency)
* Compressed cel style images or animations
* Polygon fiilling, especially with multiple layers instead of merging spans into 1 layer
* Cheap enough to run in hi-res?