65816 Overview - Revision history

Gadget: /* Upgrading */

2024-12-28T01:52:15Z

Upgrading

← Older revision		Revision as of 21:52, 27 December 2024
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	= Upgrading =		= Upgrading =
	The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:		The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:
	* You must use a 65C816SP part; slower models will not work.		* You must use a 3v 65C816SP part; slower models will not work.
	* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.		* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

Gadget: /* Introduction */ Slightly more accurate working.

2024-12-28T01:48:12Z

Introduction: Slightly more accurate working.

← Older revision		Revision as of 21:48, 27 December 2024
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	The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!		The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

	Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended ~~data transfers~~. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.		Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended and indexed extended addressing. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

	= Upgrading =		= Upgrading =

97.113.38.170: more URL formatting nonsense.

2024-06-02T21:10:28Z

more URL formatting nonsense.

← Older revision		Revision as of 17:10, 2 June 2024
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	</nowiki>		</nowiki>

	* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: ~~[C256\|~~https://wiki.c256foenix.com/index.php?title=C256]		* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: https://wiki.c256foenix.com/index.php?title=C256

	= Kernel Support =		= Kernel Support =

97.113.38.170: The C256 wiki link needs a different format.

2024-06-02T21:09:32Z

The C256 wiki link needs a different format.

← Older revision		Revision as of 17:09, 2 June 2024
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	</nowiki>		</nowiki>

	* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: [[C256\|https://wiki.c256foenix.com/index.php?title=C256]]		* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: [C256\|https://wiki.c256foenix.com/index.php?title=C256]

	= Kernel Support =		= Kernel Support =

97.113.38.170: Added link to the C256 wiki for users experimenting with the 816e FPGA load for the Jr.

2024-06-02T21:08:34Z

Added link to the C256 wiki for users experimenting with the 816e FPGA load for the Jr.

← Older revision		Revision as of 17:08, 2 June 2024
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	+ .cpu "w65c02"		+ .cpu "w65c02"
	</nowiki>		</nowiki>

			* If you are experimenting with the F816e 24-bit 816 load for the Rev B Jr's FPGA, see the 24-bit wiki for more details: [[C256\|https://wiki.c256foenix.com/index.php?title=C256]]

	= Kernel Support =		= Kernel Support =

Gadget: /* Programming */

2023-12-21T20:11:21Z

Programming

← Older revision		Revision as of 16:11, 21 December 2023
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	= Programming =		= Programming =

	* The ~~stanfard~~ FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.		* The standard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
	* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.		* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.
	<nowiki>		<nowiki>

Gadget: /* Upgrading */

2023-12-21T06:10:02Z

Upgrading

← Older revision		Revision as of 02:10, 21 December 2023
Line 5:		Line 5:

	= Upgrading =		= Upgrading =
	The 65c02 in the F256 ~~map~~ be upgraded to a 65816 with the following caveats:		The 65c02 in the F256 may be upgraded to a 65816 with the following caveats:
	* You must use a 65C816SP part; slower models will not work.		* You must use a 65C816SP part; slower models will not work.
	* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.		* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

Gadget: Added kernel notes.

2023-12-21T06:07:56Z

Added kernel notes.

← Older revision		Revision as of 02:07, 21 December 2023
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	* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.		* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

	== Programming ==		= Programming =

	* The stanfard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.		* The stanfard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
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	+ .cpu "w65c02"		+ .cpu "w65c02"
	</nowiki>		</nowiki>

			= Kernel Support =
			* The [[MicroKernel]] does not support the 816 running in native mode. You can still use the enhanced instructions in emulation mode, and you can temporarily switch to native mode while interrupts are disabled, but note that such software will not run correctly on standard 65c02 machines.
			* The [[OpenFNXKernal]] endeavors to function correctly in both modes.

	= Historical Notes =		= Historical Notes =

Gadget: Structured description of the 816 option.

2023-12-21T05:56:20Z

Structured description of the 816 option.

← Older revision		Revision as of 01:56, 21 December 2023
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	The W65C816 (~~also~~ 65C816 or ~~65816~~) is a 16-bit ~~microprocessor~~ (~~MPU~~) ~~developed~~ and ~~sold~~ by the ~~Western Design Center~~ (~~WDC~~). Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.		= Introduction =
			The Western Design Center W65C816 (aka 65C816, 65816, or just 816) is 16-bit upgrade to the 65c02. By default, it starts up in emulation mode, which is compatible with a WDC 65C02 without the extended Rockwell instructions. In emulation mode, all registers are 8 bits wide, the zero page is locked to $00xx, the stack is locked to $01xx, and the flags and interrupt vectors behave as expected for a 65c02. Note that all of the the additional 816 instructions are actually usable in this mode!

			Switching to "native" mode, the S register becomes 16 bits wide, the A register can be switched between either 8 or 16 bits wide, X and Y (always together) can be switched between either 8 or 16 bits wide, and the zero page becomes a direct page which may be placed anywhere in the first 64k. Additionally, the K registers sets the bank used for code, and the B register sets the bank used for extended data transfers. Note however, that with the standard FPGA load, the upper 8-bits of all 24-bit addresses are treated by the hardware as if they were set to zero. Finally, interrupts vector to an entirely different set of vectors, making it possible for interrupts to function correctly in either mode.

			= Upgrading =
			The 65c02 in the F256 map be upgraded to a 65816 with the following caveats:
			* You must use a 65C816SP part; slower models will not work.
			* The 816 does not support the extended Rockwell 6502 instructions (BBS/BBR/SMB/RMB); these instructions must be avoided for software to maintain 816 compatibility. Software using these instructions will not run correctly on a 65816.

			== Programming ==

			* The stanfard FPGA load ignores the upper 8-bits of all 24-bit transfers; you will still need to use the MMU to access more than 64k.
			* If you are not booting to the stock MicroKernel, you will need to tell the FPGA that you have an 816 installed.
			<nowiki>
			; If this is a 65816, switch pin 3 from an input
			; (for PHI0-out) to a 1 output (for ABORTB-in).
			.cpu "65816"
			clc
			xce
			bcc +
			sec
			xce
			stz $1
			lda #$03
			sta $d6b0
			+ .cpu "w65c02"
			</nowiki>

			= Historical Notes =

			Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

	The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.		The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

KoolKiwi at 21:09, 17 December 2023

2023-12-17T21:09:31Z

← Older revision		Revision as of 17:09, 17 December 2023
Line 1:		Line 1:
	The W65C816 (also 65C816 or 65816) is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.		The W65C816 (also 65C816 or 65816) is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816 is an enhanced version of the WDC W65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU.

	The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the ~~F526~~.		The 65C816 is a CPU option supported by the Foenix F256, that can be dropped-in, in place pf the default W65C02 processor supplied with the F256.

	The 65 in the part's designation comes from its 65C02 compatibility mode, and the 816 signifies that the MPU has selectable 8- and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24 bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new ~~electrical~~ signals for improved system hardware management.		The "65" in the part's designation comes from its 65C02 compatibility mode, and the "816" signifies that the MPU has selectable 8-bit and 16-bit register sizes. In addition to the availability of 16-bit registers, the W65C816 processor itself extends potential memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory. It has an enhanced instruction set and a 16-bit stack pointer, as well as several new control signals for improved system hardware management.

	Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.		Despite allowing 24-bit addressing, a 65816 installed in a Foenix F256 still utilises the same 16-bit physical address space of the original W65C02 processor.
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	At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.		At reset, the W65C816 starts in "emulation mode", meaning it substantially behaves as a 65C02. In fact, a 65816 in default power-up "emulation mode" is cycle-accurate with the original MOS 6502 processor, whereas the W65C02 differs on some instructions.

	User programs can then switch the W65C816 ~~may be switched~~ to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.		User programs can then switch the W65C816 to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software.

	However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.		However, unlike the DIP40 version of the W65C02, which is more-or-less a pin-compatible replacement for its NMOS ancestor (excepting mostly pin 1 - Vss / VPB), the DIP40 W65C816 is not directly pin-compatible with any other 6502 family MPU.

	The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).		The W65C816 pin differences are mostly around the clock pins and some control pins. Despite this, the W65C816 can be a drop-in replacement for the W65C02 on the Foenix F256 series. No FPGA upgrade is necessary when in emulation mode (#).