FPU Accumulator - Revision history

WF at 06:31, 8 March 2026

2026-03-08T06:31:08Z

@@ Line 16: / Line 16: @@
 '''TODO''' - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness? Should all integer commands respect a single signedness control flag?
 {| class="wikitable"
-|+Integer control flag
+|+Config registers
 !7
 !6
@@ Line 27: / Line 46: @@
 !0
 |-
 |Signed
 |64bit reg0
 |—
 | colspan="5" |Fixed point frac bits (0-31)
 |}
 {| class="wikitable"
@@ Line 53: / Line 103: @@
 |Reg
 |(A, Reg) = (Reg, A)
 |}
 {| class="wikitable"
@@ Line 217: / Line 287: @@
 |Reg
 |A = Ceil(A), Reg = Frac(A)  (options?)
 |}
 {| class="wikitable"

WF at 09:14, 20 February 2026

2026-02-20T09:14:52Z

@@ Line 344: / Line 344: @@
 |Ignored
 |A = Abs(A)
 |}

WF at 21:31, 3 February 2026

2026-02-03T21:31:49Z

@@ Line 1: / Line 1: @@
 This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.
-There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets, but more complicated bus mastering, steal cpu cycles) and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.
+There are 256 32-bit zeropage-like registers and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.
 Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.
@@ Line 13: / Line 15: @@
 Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.
-'''TODO''' - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness?
+'''TODO''' - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness? Should all integer commands respect a single signedness control flag?
 {| class="wikitable"
 |+Shared Operations

WF at 08:02, 29 December 2025

2025-12-29T08:02:27Z

← Older revision		Revision as of 04:02, 29 December 2025
Line 5:		Line 5:
	Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.		Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.

	Status bits (TBD) are available to read, with various errors, and Z/N/V/C flags just like the 6502.		Status bits (TBD) are available to read, with various errors, and integer as well as fp Z/N/V/C flags just like the 6502. V and C are only for integer ops.

			* Overflow/underflow (fp/int range, as well as f2i)
			* Division by zero
			* Int conversion lost fractional portion

	Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.		Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.
Line 185:		Line 189:
	\|		\|
	\|A = Arccos(A)		\|A = Arccos(A)
			\|-
			\|
			\|FFLOOR
			\|Reg
			\|A = Floor(A), Reg = Frac(A) (options?)
			\|-
			\|
			\|FCEIL
			\|Reg
			\|A = Ceil(A), Reg = Frac(A) (options?)
	\|}		\|}
	{\| class="wikitable"		{\| class="wikitable"

WF at 18:46, 26 December 2025

2025-12-26T18:46:38Z

← Older revision		Revision as of 14:46, 26 December 2025
Line 83:		Line 83:
	\|Reg		\|Reg
	\|A = Max(A, Reg)		\|A = Max(A, Reg)
			\|-
			\|
			\|FABS
			\|Ignored
			\|A = Abs(A)
	\|-		\|-
	\| colspan="4" \|Maybe		\| colspan="4" \|Maybe
Line 302:		Line 307:
	\|Reg		\|Reg
	\|A = Max(A, Reg)		\|A = Max(A, Reg)
			\|-
			\|
			\|IABS
			\|Ignored
			\|A = Abs(A)
	\|}		\|}

WF at 08:29, 26 December 2025

2025-12-26T08:29:48Z

@@ Line 1: / Line 1: @@
 This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.
-There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.
+There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets, but more complicated bus mastering, steal cpu cycles) and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.
 Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.
@@ Line 113: / Line 113: @@
+|
 |FNEG
 |0
-|A = -A (FRSUB instead)
+|A = Sin(A)
 |}
 {| class="wikitable"
@@ Line 147: / Line 212: @@
 |Reg
 |A = Reg - A
 |-
+|
 |IMUL
 |Reg
-|A = A * Reg
+|A = A * Reg (TBD - 64-bit result? Could auto-write Reg 0?)
 |-
+|
 |IDIV
 |Reg
-|A = A / Reg
+|A = A / Reg (TBD - combined DIVMOD? 64/32 DIV?)
 |-
+|

WF at 08:13, 26 December 2025

2025-12-26T08:13:01Z

← Older revision		Revision as of 04:13, 26 December 2025
Line 1:		Line 1:
	This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.		This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.

	There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of ~~these~~ can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.		There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of the registers can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.

	Commands are issued by writing a byte to an I/O location. The location identifies the command, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.		Commands are issued by writing a byte to an I/O location. The location identifies the command to trigger, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.

	Status bits (TBD) are available to read, with various errors, and Z/N/V/C flags just like the 6502.		Status bits (TBD) are available to read, with various errors, and Z/N/V/C flags just like the 6502.

WF: Created page with "This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided. There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of these can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values. Commands are issued by writin..."

2025-12-26T08:11:56Z

Created page with "This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided. There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of these can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values. Commands are issued by writin..."

New page

This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided.

There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of these can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values.

Commands are issued by writing a byte to an I/O location. The location identifies the command, and the byte written is often a selector for which register number to use, sometimes a literal integer value, or ignored.

Status bits (TBD) are available to read, with various errors, and Z/N/V/C flags just like the 6502.

Set the integer fixed point location (TBD) which affects multiply, divide, and conversion with floats.

'''TODO''' - should there be separate signed & unsigned variants of integer operations (including F2I), or a mode bit for signedness?
{| class="wikitable"
|+Shared Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|LOAD
|Reg
|A = Reg
|-
|
|STORE
|Reg
|Reg = A
|-
|
|SWAP
|Reg
|(A, Reg) = (Reg, A)
|}
{| class="wikitable"
|+Floating Point Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|FADD
|Reg
|A = A + Reg
|-
|
|FSUB
|Reg
|A = A - Reg
|-
|
|FRSUB
|Reg
|A = Reg - A
|-
|
|FMUL
|Reg
|A = A * Reg
|-
|
|FDIV
|Reg
|A = A / Reg
|-
|
|FRDIV
|Reg
|A = Reg / A
|-
|
|F2I
|Signed flag
|A = Int(A) or UInt(A)
|-
|
|FMIN
|Reg
|A = Min(A, Reg)
|-
|
|FMAX
|Reg
|A = Max(A, Reg)
|-
| colspan="4" |Maybe
|-
|
|FADDB
|Byte
|A = A + Val
|-
|
|FSUBB
|Byte
|A = A - Val
|-
|
|FMULB
|Byte
|A = A * Val
|-
|
|FDIVB
|Byte
|A = A / Val
|-
|
|FCLR
|Ignored
|A = 0.0 (LOAD instead)
|-
|
|FNEG
|0
|A = -A (FRSUB instead)
|}
{| class="wikitable"
|+Integer Operations
!Cmd #
!Name
!Parameter
!Description
|-
|
|IADD
|Reg
|A = A + Reg
|-
|
|IADDC
|Reg
|A = A + Reg + C
|-
|
|ISUB
|Reg
|A = A - Reg
|-
|
|ISUBC
|Reg
|A = A - Reg - !C
|-
|
|IRSUB
|Reg
|A = Reg - A
|-
|
|IMUL
|Reg
|A = A * Reg
|-
|
|IDIV
|Reg
|A = A / Reg
|-
|
|IMOD
|Reg
|A = A % Reg
|-
|
|ICMP
|Reg
|Status = A - Reg
|-
|
|INEG
|0
|A = -A
|-
|
|IAND
|Reg
|A = A & Reg
|-
|
|IOR
|Reg
|<nowiki>A = A | Reg</nowiki>
|-
|
|IXOR
|Reg
|A = A ^ Reg
|-
|
|I2F
|Signed Flag
|A = Float(Int(A)) or Float(UInt(A))
|-
|
|ISHL
|Count
|A = A << Value
|-
|
|ISHR
|Count
|A = A >> Value
|-
|
|ISSHR
|Count
|A = A >>(signed) Value
|-
|
|IROLL
|Count
|<nowiki>A = (A << Count) | (A >> (32 - Count))</nowiki>
|-
|
|IUMIN
|Reg
|A = Min(A, Reg)
|-
|
|ISMIN
|Reg
|A = Min(A, Reg)
|-
|
|IUMAX
|Reg
|A = Max(A, Reg)
|-
|
|ISMAX
|Reg
|A = Max(A, Reg)
|}