IO Pages - Revision history

WF: /* $D000: Master Control Registers */

2026-03-09T01:01:53Z

$D000: Master Control Registers

@@ Line 61: / Line 61: @@
 ===== $D000: VICKY Config =====
-====== $D000: Master Control Registers ======
+====== $D000: Master Control Registers 0-1 ======
 {| class="wikitable"
 !MMU
@@ Line 93: / Line 93: @@
 |RW
 |MSTR_CTRL_1
-|—
+|MT_OVLY*
-|—
+|MEMTEXT*
 |FON_SET
 |FON_OVLY
@@ Line 125: / Line 125: @@
 '''FON_SET''': Chooses font set 0 or 1
 ====== $D002: Layers ======
@@ Line 230: / Line 234: @@
 |—
 | colspan="5" |SIZE_Y
 |}
@@ Line 3,091: / Line 3,124: @@
 |}
 Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

2026-03-09T00:48:10Z

$D180: Bresenham Lines

← Older revision		Revision as of 20:48, 8 March 2026
Line 446:		Line 446:
	\|}		\|}

	===== $D180: Bresenham Lines =====		===== $D180: Bresenham Lines (Core2x Only) =====
	{\| class="wikitable"		{\| class="wikitable"
	!MMU		!MMU
Line 521:		Line 521:
	\| colspan="8" \|Y1		\| colspan="8" \|Y1
	\|}		\|}
			This shares timing with the 2nd bank of sprites, so the two are mutually exclusive.

	BASIC Example:		BASIC Example:
	1000 proc hwline(x0,y0,x1,y1,col)		1000 proc hwline(x0,y0,x1,y1,col)

2026-03-09T00:36:40Z

$D100: Bitmaps

@@ Line 445: / Line 445: @@
 | colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
 |}
 ===== $D200: Tilemaps =====

2026-03-09T00:18:27Z

$DF00: DMA Controller

← Older revision		Revision as of 20:18, 8 March 2026
Line 2,871:		Line 2,871:
	\| colspan="8" \|Destination stride (16-bit, 2D mode)		\| colspan="8" \|Destination stride (16-bit, 2D mode)
	\|}		\|}
	<nowiki>*</nowiki> = Experimental in wf-dma cores		<nowiki>*</nowiki> = Experimental in wf-dma cores, masks out $00 bytes from the source data, skipping writes for those pixels.

	DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.		DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

2026-03-08T21:17:49Z

$DF00: DMA Controller

← Older revision		Revision as of 17:17, 8 March 2026
Line 2,804:		Line 2,804:
	\|—		\|—
	\|—		\|—
	\|—		\|<u>''MASK0''</u>*
	\|INT_EN		\|INT_EN
	\|FILL		\|FILL
Line 2,871:		Line 2,871:
	\| colspan="8" \|Destination stride (16-bit, 2D mode)		\| colspan="8" \|Destination stride (16-bit, 2D mode)
	\|}		\|}
			<nowiki>*</nowiki> = Experimental in wf-dma cores

	DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.		DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

2026-02-25T23:52:28Z

$D018: Raster

← Older revision		Revision as of 19:52, 25 February 2026
Line 379:		Line 379:
	\|2		\|2
	\|$002		\|$002
	\|Core2x: DMA starts halfway through line (8192 SRAM cycles from SOF)		\|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
	\|-		\|-
	\|43		\|43

2026-02-25T23:51:40Z

$D018: Raster

← Older revision		Revision as of 19:51, 25 February 2026
Line 383:		Line 383:
	\|43		\|43
	\|$02B		\|$02B
	\|DMA safety ~~zone~~, ~~disabled~~ from here		\|DMA safety margin, pauses from here
	\|-		\|-
	\|45		\|45

2026-02-25T23:49:12Z

$D018: Raster

← Older revision		Revision as of 19:49, 25 February 2026
Line 375:		Line 375:
	\|0		\|0
	\|$000		\|$000
	\|Start of frame, VBLANK, and non-~~Core2xDMA~~		\|Start of frame, VBLANK, and non-Core2x DMA
	\|-		\|-
	\|2		\|2
	\|$002		\|$002
	\|Core2x: DMA starts halfway through ~~here~~ (8192 SRAM cycles from SOF)		\|Core2x: DMA starts halfway through line (8192 SRAM cycles from SOF)
	\|-		\|-
	\|43		\|43

2026-02-25T23:47:59Z

$D018: Raster

← Older revision		Revision as of 19:47, 25 February 2026
Line 375:		Line 375:
	\|0		\|0
	\|$000		\|$000
	\|Start of frame, VBLANK, and DMA		\|Start of frame, VBLANK, and non-Core2xDMA
			\|-
			\|2
			\|$002
			\|Core2x: DMA starts halfway through here (8192 SRAM cycles from SOF)
	\|-		\|-
	\|43		\|43

2026-02-25T23:19:48Z

$D018: Raster

@@ Line 366: / Line 366: @@
 |LINT_L
 | colspan="8" |Line interrupt line (12-bit)
 |}