1BitFeverDreams: new channel wide registers and operator wide registers, and the mapping for all 18 channels when using operator wide regs

2025-11-25T06:24:59Z

new channel wide registers and operator wide registers, and the mapping for all 18 channels when using operator wide regs

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1BitFeverDreams: /* The YMF262 is inside the FPGA of some machines */

2025-08-24T15:39:55Z

The YMF262 is inside the FPGA of some machines

← Older revision		Revision as of 11:39, 24 August 2025
Line 3:		Line 3:
	The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators<br>		The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators<br>

			=== F256 registers for 6502, 65816, 6809(?) cores ===
	{\| class="wikitable"		{\| class="wikitable"
	\|+		\|+

1BitFeverDreams: /* The YMF262 is inside the FPGA of some machines */ examples

2025-08-24T15:39:01Z

The YMF262 is inside the FPGA of some machines: examples

← Older revision		Revision as of 11:39, 24 August 2025
Line 21:		Line 21:
	\|Register for addressing ports 0x100 to 0x1FF		\|Register for addressing ports 0x100 to 0x1FF
	\|}		\|}

			===== Usage: =====
			When targetting a port in the 0x000 - 0x0FF range, send the port byte to 0xD580, then its data byte to 0x581.

			When targetting a port in the 0x100 - 0x1FF range, send the port byte ''masked with 0x0FF to 0xD582,'' then its data byte to 0xD581''.''

			Example 1: to star the chip using port 0x01, send 0x01 to 0xD580, then 0x01 to 0xD581.

			Example 2: to enable OPL3 using port 0x105, send 0x05 to 0xD582, then 0x01 to 0xD581.

	=== Chip wide ports ===		=== Chip wide ports ===

1BitFeverDreams: Created page with "== The YMF262 is inside the FPGA of some machines == The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators
{| class="wikitable" |+ !Register Name !Address !Description |- |OPL_ADDR_L |0xD580 |Register for addressing ports 0x000 to 0x0FF |- |OPL_DATA |0xD581 |Data register for all ports |- |OPL_ADDR_H |0xD582 |R..."

2025-08-24T15:34:35Z

Created page with "== The YMF262 is inside the FPGA of some machines == The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators {| class="wikitable" |+ !Register Name !Address !Description |- |OPL_ADDR_L |0xD580 |Register for addressing ports 0x000 to 0x0FF |- |OPL_DATA |0xD581 |Data register for all ports |- |OPL_ADDR_H |0xD582 |R..."

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== The YMF262 is inside the FPGA of some machines ==

The F256 machines, except the F256Jr., have in their Beatrix FPGA a YMF262 capable of Yamaha OPL3 that uses up to 36 operators. You can also use it in compatible OPL2 that uses a subset of up to 18 operators 

{| class="wikitable"
|+
!Register Name
!Address
!Description
|-
|OPL_ADDR_L
|0xD580
|Register for addressing ports 0x000 to 0x0FF
|-
|OPL_DATA
|0xD581
|Data register for all ports
|-
|OPL_ADDR_H
|0xD582
|Register for addressing ports 0x100 to 0x1FF
|}

=== Chip wide ports ===
{| class="wikitable"
|+
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Test Register / Waveform Select Enable
|0x01
|Must be used to "start the chip"
| colspan="2" | Test Register
| Wave Select Enable
| colspan="5" | Test Register
|-
| colspan="2" |
| colspan="9" | Set all Test Register bits to 0 to start the chip. B5 clear = all sine waves B5 set= enables wave choices in 0xE0-F5
|-
|Timer 1 Count
|0x02
|8bit timer with resolution of 80 us.
|
|
|
|
|
|
|
|
|-
| colspan="2" |
| colspan="9" | If overflow occurs, status register is set and preset value is loaded
|-
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Timer 2 Count
|0x03
|8bit timer with resolution of 320 us.
|
|
|
|
|
|
|
|
|-
| colspan="2" |
| colspan="9" | If overflow occurs, status register is set and preset value is loaded
|-
|IRQ-Reset/Mask/Start
|0x04
|Timer controls
|Reset
|T1Mask
|T2Mask
| -
| -
| -
|T2Start
|T1Start
|-
| colspan="2" |
| colspan="9" | B7 resets and IRQ flags status reg and ignore all others when this is set 
B6 timer 1 mask. status reg is not affected in overflow 
B5 timer 2 mask. same for timer2 
B1 Timer 2 start. timer on/off 
B0 Timer 1 start, same
|-
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Four-Operator Enable
|0x104
| Sets up four-operator channels
| -
| -
| ChB
| ChA
| Ch9
| Ch2
| Ch1
| Ch0
|-
| colspan="2" |
| colspan="9" | When fully set 0, 18 two-operator pairs are formed. When non-zero, four-operators are formed at specific locations 
B5: channels 11-14 (decimal) are grouped 
B4: channels 10-13 
B3: channels 9-12 
B2: channels 2-5 
B1: channels 1-4 
B0: channels 0-3
|-
|OPL3 Mode Enable
|0x105
| enables OPL3 extensions
| -
| -
| -
| -
| -
| -
| -
| Enable
|-
| colspan="2" |
| colspan="9" | set B0 to enable 36 operators, 4-OP synth, 8 waveforms, stereo output. When cleared, OPL2 is enabled.
|-
!Port Name
!Port Address
!Description
!B7
!B6
!B5
!B4
!B3
!B2
!B1
!B0
|-
|Tremolo/Vibrato/Percussion
|0xBD
| Bits 0-4 are treated as key-on/key-offs.
| Tre
| Vib
| Per
| BassDrum
| SnareDrum
| Tom-Tom
| Cymbal
| Hi-Hat
|-
| colspan="2" |
| colspan="9" | B7 and B6 set = more present effect. 
When using B0-B4, key-on in channels 6,7,8 and their fnums have to be cleared! Their ADSR must be appropriate 
This register is only used in OPL2 lower half, it does not affect higher half OPL3.
|}

=== Channel wide ports ===

to be continued

=== Operator wide ports ===

to be continued

Use the OPL3 YMF262 - Revision history

1BitFeverDreams: new channel wide registers and operator wide registers, and the mapping for all 18 channels when using operator wide regs

1BitFeverDreams: /* The YMF262 is inside the FPGA of some machines */

1BitFeverDreams: /* The YMF262 is inside the FPGA of some machines */ examples