IO Pages: Difference between revisions

From Foenix F256 / Wildbits/K2 Wiki
Jump to navigationJump to search
VisualWikitext
(in progress)
 
(55 intermediate revisions by 2 users not shown)
Line 1: Line 1:
More detailed information is found in the [[Manuals]].
More detailed information is found in the [[Manuals]].


=== Notes ===
== Notes ==
'''SRAM Address''': The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, Core2x has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 24-bit CPU-visible addresses.
<span id="SRAM Address>'''SRAM Address'''</span>: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.


'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
'''Model names''': Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.
<span id="BGR">'''BGR'''</span>: A 3-byte color entry in Blue, Green, Red order.
<span id="BGRx">'''BGRx'''</span>: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.
<span id="RGB">'''RGB'''</span>: A 3-byte color entry in Red, Green, Blue order, as things should be.


== IO Page 0 ==
== IO Page 0 ==
====== $C000: Gamma Lookup ======
{| class="wikitable"
{| class="wikitable"
|+Gamma Lookup
!MMU
!MMU
!Flat
!Flat
Line 17: Line 24:
|$C000 - $C0FF
|$C000 - $C0FF
|$F0:0000 - $F0:00FF
|$F0:0000 - $F0:00FF
|RW
|
|
|
|Blue gamma conversion table
|Blue conversion table
|-
|-
|$C400 - $C4FF
|$C400 - $C4FF
|$F0:0400 - $F0:04FF
|$F0:0400 - $F0:04FF
|RW
|
|
|
|Green gamma conversion table
|Green conversion table
|-
|-
|$C800 - $C8FF
|$C800 - $C8FF
|$F0:0800 - $F0:08FF
|$F0:0800 - $F0:08FF
|RW
|
|
|Red gamma conversion table
|}
Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.
====== $CC00: Mouse Pointer Bitmap ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$CC00 - $CCFF
|$F0:0C00 - $F0:0CFF
|RW
|
|
|Red conversion table
|Mouse pointer bitmap (16×16 greyscale bytes)
|}
|}
This is currently mirrored 4 times in $CC00 - $CFFF.


=== Master Control Registers ($D0xx, $F0:10xx) ===
===== $D000: VICKY Config =====
 
====== $D000: Master Control Registers ======
{| class="wikitable"
{| class="wikitable"
|+Master Control
!MMU
!MMU
!Flat
!Flat
Line 99: Line 125:


'''FON_SET''': Chooses font set 0 or 1
'''FON_SET''': Chooses font set 0 or 1
====== $D002: Layers ======
{| class="wikitable"
{| class="wikitable"
|+Layer Configuration
!MMU
!MMU
!Flat
!Flat
!R/W
!R/W
!Name
!7
!7
!6
!6
Line 114: Line 142:
|-
|-
|$D002
|$D002
|$F0:1002
|RW
|
|
|RW
|—
|—
| colspan="3" |Layer 1
| colspan="3" |Layer 1
Line 122: Line 151:
|-
|-
|$D003
|$D003
|$F0:1003
|RW
|
|
|RW
|—
|—
|—
|—
Line 130: Line 160:
|—
|—
| colspan="3" |Layer 2
| colspan="3" |Layer 2
|}
There are 6 configurable graphics maps that can be placed into any of the 3 visible layers. Layer 0 is the front graphics layer.
{| class="wikitable"
|+Layer Codes
!Code
!Graphics Map
|-
|0
|Bitmap 0
|-
|1
|Bitmap 1
|-
|2
|Bitmap 2
|-
|-
|
|
|
|
|-
|
|4
|Values
|Tilemap 0
| colspan="8" |0-2: Bitmap 0-2
|-
4-6: Tilemap 0-2
|5
|Tilemap 1
|-
|6
|Tilemap 2
|}
|}
====== $D004: Border ======
{| class="wikitable"
{| class="wikitable"
|+Border
!MMU
!MMU
!Flat
!Flat
Line 174: Line 185:
|-
|-
|$D004
|$D004
|
|$F0:1004
|RW
|RW
|BRDR_CTRL
|BRDR_CTRL
Line 185: Line 196:
|-
|-
|$D005
|$D005
|
|$F0:1005
|RW
|RW
|BRDR_BLUE
|BRDR_BLUE
Line 191: Line 202:
|-
|-
|$D006
|$D006
|
|$F0:1006
|RW
|RW
|BRDR_GREEN
|BRDR_GREEN
Line 197: Line 208:
|-
|-
|$D007
|$D007
|
|$F0:1007
|RW
|RW
|BRDR_RED
|BRDR_RED
Line 203: Line 214:
|-
|-
|$D008
|$D008
|
|$F0:1008
|RW
|RW
|BRDR_WIDTH
|BRDR_WIDTH
Line 212: Line 223:
|-
|-
|$D009
|$D009
|
|$F0:1009
|RW
|RW
|BRDR_HEIGHT
|BRDR_HEIGHT
Line 220: Line 231:
| colspan="5" |SIZE_Y
| colspan="5" |SIZE_Y
|}
|}
====== $D00D: Background ======
{| class="wikitable"
{| class="wikitable"
|+Background Color
!MMU
!MMU
!Flat
!Flat
Line 236: Line 248:
|-
|-
|$D00D
|$D00D
|
|$F0:100D
|RW
|RW
|BGND_BLUE
|BGND_BLUE
Line 242: Line 254:
|-
|-
|$D00E
|$D00E
|
|$F0:100E
|RW
|RW
|BGND_GREEN
|BGND_GREEN
Line 248: Line 260:
|-
|-
|$D00F
|$D00F
|
|$F0:100F
|RW
|RW
|BGND_RED
|BGND_RED
| colspan="8" |Background color Red component
| colspan="8" |Background color Red component
|}
|}
====== $D010: Text Cursor ======
{| class="wikitable"
{| class="wikitable"
|+Text Cursor
!MMU
!MMU
!Flat
!Flat
Line 269: Line 282:
|-
|-
|$D010
|$D010
|
|$F0:1010
|RW
|RW
|CCR
|CCR
|
|—
|
|—
|
|—
|
|—
|FLASH_DIS
|FLASH_DIS
| colspan="2" |RATE
| colspan="2" |RATE
|ENABLE
|ENABLE
|-
|
|
|
|RATE
| colspan="8" |0: 1 second
1: 1/2 second
2: 1/4 second
3: 1/8 second
|-
|-
|$D012
|$D012
|
|$F0:1012
|RW
|RW
|CCH
|CCH
| colspan="8" |Cursor character code
| colspan="8" |Cursor character code
|-
|-
|$D014 - $D015
|$D014
|
|$F0:1014
|RW
|RW
|CURX
|CURX
| colspan="8" |Cursor X position (16-bit)
| colspan="8" |Cursor X position (16-bit)
|-
|-
|$D016 - $D017
|$D016
|
|$F0:1016
|RW
|RW
|CURY
|CURY
| colspan="8" |Cursor Y position (16-bit)
| colspan="8" |Cursor Y position (16-bit)
|}
|}
====== $D018: Raster ======
{| class="wikitable"
{| class="wikitable"
|+Cursor Flash Rate
!Value
!Rate
|-
|0
|1 second
|-
|1
|1/2 second
|-
|2
|1/4 second
|-
|3
|1/8 second
|}
{| class="wikitable"
|+Raster
!MMU
!MMU
!Flat
!Flat
Line 330: Line 336:
!0
!0
|-
|-
|$D018 - $D019
|$D018
|
|$F0:1018
|R
|R
|RAST_COL
|RAST_COL
| colspan="8" |Raster current column (12-bit)
| colspan="8" |Raster current column (12-bit)
|-
|-
|$D01A - $D01B
|$D01A
|
|$F0:101A
|R
|R
|RAST_ROW
|RAST_ROW
Line 343: Line 349:
|-
|-
|$D018
|$D018
|
|$F0:1018
|W
|W
|LINT_CTRL
|LINT_CTRL
|
|—
|
|—
|
|—
|
|—
|
|—
|
|—
|
|—
|ENABLE
|ENABLE
|-
|-
|$D019 - $D01A
|$D019
|
|$F0:1019
|W
|W
|LINT_L
|LINT_L
| colspan="8" |Line interrupt line (12-bit)
| colspan="8" |Line interrupt line (12-bit)
|}
{| class="wikitable"
|+Raster line numbers in a frame
!Dec
!Hex
!Description
|-
|0
|$000
|Start of frame, VBLANK, and  non-Core2x DMA
|-
|2
|$002
|Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
|-
|43
|$02B
|DMA safety margin, pauses from here
|-
|45
|$02D
|First visible line
|-
|524
|$20C
|Last visible line, last line of frame
|}
|}


=== Bitmap Control Registers ($D1xx, $F0:11xx) ===
===== $D100: Bitmaps =====
{| class="wikitable"
{| class="wikitable"
|+Bitmaps
!MMU
!MMU
!Flat
!Flat
Line 379: Line 410:
|-
|-
|$D100
|$D100
|$F0:1100
|
|
|RW
|
|
| colspan="8" |Bitmap 0
|-
|$D108
|$F0:1108
|
|
|
|
| colspan="8" |Bitmap 1
|-
|$D110
|$F0:1110
|
|
|
|
| colspan="8" |Bitmap 2
|-
|
|
| +0
|RW
|
|—
|—
|—
|—
|—
| colspan="2" |CLUT
| colspan="2" |CLUT
|ENABLE
|ENABLE
|-
|-
|$D101 - $D103
|
|
| +1
|RW
|RW
|
|
| colspan="8" |SRAM Address of bitmap 0 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of pixels (24-bit)
|}
 
===== $D200: Tilemaps =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D108
|$D200
|
|$F0:1200
|RW
|
|
|
|
| colspan="8" |Tilemap 0
|-
|$D20C
|$F0:120C
|
|
|
|
| colspan="8" |Tilemap 1
|-
|$D218
|$F0:1218
|
|
| colspan="8" |Tilemap 2
|-
|
|
| +$00
|W
|
|
| colspan="2" |CLUT
|—
|—
|—
|TILE_SIZE_8
|—
|—
|—
|ENABLE
|ENABLE
|-
|-
|$D109 - $D10B
|
|
|RW
| +$01
|W
|
|
| colspan="8" |SRAM Address of bitmap 1 pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile map entries (24-bit) '''**'''
|-
|-
|$D110
|
|
|RW
| +$04
|W
|
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|
|
| +$06
|W
|
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|
|
| +$08
|W
|
| colspan="4" rowspan="2" |Tile Scroll X[3:0]
| colspan="4" |16x16 Pixel Scroll SSX
|-
|
|
|
|
| colspan="2" |CLUT
|ENABLE
|-
|$D111 - $D103
|
|
|RW
|
|
| colspan="8" |SRAM Address of bitmap 2 pixels (24-bit)
|—
|}
| colspan="3" |8x8 SSX
 
=== Tilemap Control Registers ($D2xx, $F0:12xx) ===
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$D200
|
|
| +$09
|W
|
|
|
|—
| colspan="8" |Tilemap 0
|—
| colspan="6" |Tile Scroll X[9:4]
|-
|-
|$D20C
|
| +$0A
|W
|
| colspan="4" rowspan="2" |Tile Scroll Y[3:0]
| colspan="4" |16x16 Pixel Scroll SSY
|-
|
|
|
|
|
|
|
| colspan="8" |Tilemap 1
|—
| colspan="3" |8x8 SSY
|-
|-
|$D218
|
|
| +$0B
|W
|
|
|
|—
| colspan="8" |Tilemap 2
|—
|—
|—
| colspan="4" |Tile Scroll Y[7:4]
|}
|}
'''**''' = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.
The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.
{| class="wikitable"
{| class="wikitable"
|+Tilemap
|+Tile Map Entry
!Offset
!Offset
!R/W
!Name
!7
!7
!6
!6
Line 480: Line 571:
!0
!0
|-
|-
|$00
| +0
|W
| colspan="8" |Tile number
|
|
|
|
|TILE_SIZE_8
|
|
|
|ENABLE
|-
|-
|$01 - $03
| +1
|W
|—
|
| colspan="8" |SRAM Address of tile map entries (24-bit)
|-
|$04
|W
|
| colspan="8" |MAP_SIZE_X (8-bit)
|-
|$06
|W
|
| colspan="8" |MAP_SIZE_Y (8-bit)
|-
|$08
|W
|
| colspan="4" |X[3:0]
| colspan="4" |SSX
|-
|$09
|W
|
|—
|—
|—
|—
| colspan="6" |X[9:4]
| colspan="2" |CLUT
|-
| colspan="3" |Tileset
|$0A
|W
|
| colspan="4" |Y[3:0]
| colspan="4" |SSY
|-
|$0B
|W
|
|—
|—
|—
|—
| colspan="4" |Y[7:4]
|}
|}
====== $D280: Tilesets ======
{| class="wikitable"
{| class="wikitable"
|+Tilesets
!MMU
!MMU
!Flat
!Flat
Line 550: Line 597:
!0
!0
|-
|-
|$D280 - $D283
|$D280
|
|$F0:1280
|
|
|
|
| colspan="8" |Tileset 0
| colspan="8" |Tileset 0
|-
|-
|$D284 - $D287
|$D284
|
|$F0:1284
|
|
|
|
| colspan="8" |Tileset 1
| colspan="8" |Tileset 1
|-
|-
|$D288 - $D28B
|$D288
|
|$F0:1288
|
|
|
|
| colspan="8" |Tileset 2
| colspan="8" |Tileset 2
|-
|-
|$D28C - $D28F
|$D28C
|
|$F0:128C
|
|
|
|
| colspan="8" |Tileset 3
| colspan="8" |Tileset 3
|-
|-
|$D290 - $D293
|$D290
|
|$F0:1290
|
|
|
|
| colspan="8" |Tileset 4
| colspan="8" |Tileset 4
|-
|-
|$D294 - $D298
|$D294
|
|$F0:1294
|
|
|
|
| colspan="8" |Tileset 5
| colspan="8" |Tileset 5
|-
|-
|$D298 - $D29B
|$D298
|
|$F0:1298
|
|
|
|
| colspan="8" |Tileset 6
| colspan="8" |Tileset 6
|-
|-
|$D29C - $D29F
|$D29C
|
|$F0:129C
|
|
|
|
| colspan="8" |Tileset 7
| colspan="8" |Tileset 7
|}
{| class="wikitable"
|+Tileset
!Offset
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|0 - 2
|
| +0
|W
|W
|
|
| colspan="8" |SRAM Address of tile pixels (24-bit)
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of tile pixels (24-bit)
|-
|-
|3
|
| +3
|W
|W
|
|
|
|—
|
|—
|
|—
|
|—
|SQUARE
|SQUARE
|
|—
|
|—
|
|—
|}
|}
{| class="wikitable"
{| class="wikitable"
|+
|+Layout of Tileset Pixels
!SQUARE
!8×8 px Tiles
!16×16 px Tiles
|-
|0
|8×1024 px
|16×2048 px
|-
|1
|128×128 px
|256×256 px
|}
 
===== $D400: Sound =====
 
====== $D400: SID chips ======
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|SID_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
!MMU
!MMU
!Flat
!Flat
Line 645: Line 698:
|-
|-
|$D400
|$D400
|
|$F0:1400
|
|
|
|
Line 651: Line 704:
|-
|-
|$D500
|$D500
|$F0:1500
|
|
|
|
| colspan="8" |Right SID
|-
|
|
| colspan="8" |Right SID
| +$00
|}
|W
{| class="wikitable"
|Voice 1
|+SID Registers
| colspan="8" |Frequency (16-bit)
!Offset
|-
!R/W
|
!Name
| +$02
!7
!6
!5
!4
!3
!2
!1
!0
|-
| +$00 - $01
|W
|Voice 1
| colspan="8" |Frequency (16-bit)
|-
| +$02 - $03
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$04
| +$04
|W
|W
Line 692: Line 734:
|GATE
|GATE
|-
|-
|
| +$05
| +$05
|W
|W
|
|
| colspan="4" |ATTACK
| colspan="4" |ATTACK
|DELAY
| colspan="4" |DELAY
|
|-
|
|
|
|-
| +$06
| +$06
|W
|W
Line 707: Line 748:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
| +$07 - $08
|
| +$07
|W
|W
|Voice 2
|Voice 2
| colspan="8" |Frequency (16-bit)
| colspan="8" |Frequency (16-bit)
|-
|-
| +$09 - $0A
|
| +$09
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$0B
| +$0B
|W
|W
Line 729: Line 773:
|GATE
|GATE
|-
|-
|
| +$0C
| +$0C
|W
|W
|
|
| colspan="4" |ATTACK
| colspan="4" |ATTACK
|DELAY
| colspan="4" |DELAY
|-
|
|
|
|
|-
| +$0D
| +$0D
|W
|W
Line 744: Line 787:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
| +$0E - $0F
|
| +$0E
|W
|W
|Voice 3
|Voice 3
| colspan="8" |Frequency (16-bit)
| colspan="8" |Frequency (16-bit)
|-
|-
| +$10 - $11
|
| +$10
|W
|W
|
|
| colspan="8" |Pulse width (12-bit)
| colspan="8" |Pulse width (12-bit)
|-
|-
|
| +$12
| +$12
|W
|W
Line 766: Line 812:
|GATE
|GATE
|-
|-
|
| +$13
| +$13
|W
|W
|
|
| colspan="4" |ATTACK
| colspan="4" |ATTACK
|DELAY
| colspan="4" |DELAY
|
|-
|
|
|
|-
| +$14
| +$14
|W
|W
Line 781: Line 826:
| colspan="4" |RELEASE
| colspan="4" |RELEASE
|-
|-
|
| +$15
| +$15
|W
|W
Line 791: Line 837:
| colspan="3" |FC[2:0]
| colspan="3" |FC[2:0]
|-
|-
|
| +$16
| +$16
|W
|W
Line 796: Line 843:
| colspan="8" |FC[10:3]
| colspan="8" |FC[10:3]
|-
|-
|
| +$17
| +$17
|W
|W
Line 805: Line 853:
|FILTV1
|FILTV1
|-
|-
|
| +$18
| +$18
|W
|W
Line 814: Line 863:
| colspan="4" |VOLUME
| colspan="4" |VOLUME
|}
|}
====== $D580: OPL3 (NOT on F256Jr!) ======
Main page: [[Use the OPL3 YMF262]]
{| class="wikitable"
{| class="wikitable"
|+OPL3 Registers (NOT ON F256JR)
!MMU
!MMU
!Flat
!Flat
Line 830: Line 881:
|-
|-
|$D580
|$D580
|
|$F0:1580
|W
|W
|
|
Line 836: Line 887:
|-
|-
|$D581
|$D581
|
|$F0:1581
|W
|W
|
|
Line 842: Line 893:
|-
|-
|$D582
|$D582
|
|$F0:1582
|W
|W
|
|
| colspan="8" |Address register for ports $100 - $1FF
| colspan="8" |Address register for ports $100 - $1FF
|}
|}
====== $D600: PSGs ======
Main page: [[Use the PSG]]
Stereo separation is enabled with the '''[[IO Pages#$D6A0: System Control Registers|PSG_ST]]''' flag. By default, both PSGs go to both speakers.
{| class="wikitable"
{| class="wikitable"
|+PSG Registers
!MMU
!MMU
!Flat
!Flat
Line 863: Line 918:
|-
|-
|$D600
|$D600
|
|$F0:1600
|
|
|
|
Line 869: Line 924:
|-
|-
|$D608
|$D608
|
|$F0:1608
|
|
|
|
Line 875: Line 930:
|-
|-
|$D610
|$D610
|
|$F0:1610
|
|
|
|
| colspan="8" |PSG Right
| colspan="8" |PSG Right
|}
|}
Note the stereo separation is controlled with the '''PSG_ST''' flag.
 
====== $D620: CODEC ======
Main page: [[Use the CODEC]]
{| class="wikitable"
{| class="wikitable"
|+CODEC Registers
!MMU
!MMU
!Flat
!Flat
Line 897: Line 953:
|-
|-
|$D620
|$D620
|
|$F0:1620
|W
|W
|
|
Line 903: Line 959:
|-
|-
|$D621
|$D621
|
|$F0:1621
|W
|W
|
|
Line 910: Line 966:
|-
|-
|$D622
|$D622
|
|$F0:1622
|R
|R
|
|
Line 935: Line 991:
|START
|START
|}
|}
===== $D630: System =====
====== $D630: UART ======
{| class="wikitable"
{| class="wikitable"
|+UART Registers
!MMU
!MMU
!Flat
!Flat
Line 956: Line 1,015:
|-
|-
|$D630
|$D630
|
|$F0:1630
|R
|R
|RXD
|RXD
Line 968: Line 1,027:
|-
|-
|$D631
|$D631
|
|$F0:1631
|RW
|RW
|IER
|IER
Line 985: Line 1,044:
| colspan="9" |'''DLAB = 1'''
| colspan="9" |'''DLAB = 1'''
|-
|-
|$D630 - $D631
|$D630
|
|$F0:1630
|RW
|RW
|DL
|DL
Line 998: Line 1,057:
|-
|-
|$D632
|$D632
|
|$F0:1632
|R
|R
|IIR
|IIR
Line 1,020: Line 1,079:
|-
|-
|$D633
|$D633
|
|$F0:1633
|RW
|RW
|LCR
|LCR
Line 1,029: Line 1,088:
| colspan="2" |DATA
| colspan="2" |DATA
|}
|}
====== $D640: PS/2 ======
See: [[Use the PS/2 Mouse]]
{| class="wikitable"
{| class="wikitable"
|+PS/2 Registers
!MMU
!MMU
!Flat
!Flat
Line 1,045: Line 1,106:
|-
|-
|$D640
|$D640
|
|$F0:1640
|RW
|RW
|PS2_CTRL
|PS2_CTRL
Line 1,058: Line 1,119:
|-
|-
|$D641
|$D641
|
|$F0:1641
|RW
|RW
|PS2_OUT
|PS2_OUT
Line 1,064: Line 1,125:
|-
|-
|$D642
|$D642
|
|$F0:1642
|R
|R
|KBD_IN
|KBD_IN
Line 1,070: Line 1,131:
|-
|-
|$D643
|$D643
|
|$F0:1643
|R
|R
|MS_IN
|MS_IN
Line 1,076: Line 1,137:
|-
|-
|$D644
|$D644
|
|$F0:1644
|R
|R
|PS2_STAT
|PS2_STAT
Line 1,088: Line 1,149:
|KEMP
|KEMP
|}
|}
====== $D650: Interval Timers ======
{| class="wikitable"
{| class="wikitable"
|+Timer Registers
!MMU
!MMU
!Flat
!Flat
Line 1,104: Line 1,166:
|-
|-
|$D650
|$D650
|
|$F0:1650
|W
|W
|T0_CTR
|T0_CTR
Line 1,129: Line 1,191:
|EQ
|EQ
|-
|-
|$D651 - $D653
|$D651
|
|$F0:1651
|RW
|RW
|T0_VAL
|T0_VAL
Line 1,136: Line 1,198:
|-
|-
|$D654
|$D654
|
|$F0:1654
|RW
|RW
|T0_CMP_CTR
|T0_CMP_CTR
Line 1,148: Line 1,210:
|RECLR
|RECLR
|-
|-
|$D655 - $D657
|$D655
|
|$F0:1655
|RW
|RW
|T0_CMP
|T0_CMP
Line 1,168: Line 1,230:
|-
|-
|$D658
|$D658
|
|$F0:1658
|W
|W
|T1_CTR
|T1_CTR
Line 1,193: Line 1,255:
|EQ
|EQ
|-
|-
|$D659 - $D65B
|$D659
|
|$F0:1659
|RW
|RW
|T1_VAL
|T1_VAL
Line 1,200: Line 1,262:
|-
|-
|$D65C
|$D65C
|
|$F0:165C
|RW
|RW
|T1_CMP_CTR
|T1_CMP_CTR
Line 1,212: Line 1,274:
|RECLR
|RECLR
|-
|-
|$D65D - $D65F
|$D65D
|
|$F0:165D
|RW
|RW
|T1_CMP
|T1_CMP
| colspan="8" |CMP (24-bit)
| colspan="8" |CMP (24-bit)
|}
|}
'''WARNING:''' The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!
Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.
====== $D660: Interrupts ======
Main page: [[IRQ]], [[IRQ Programming]]
{| class="wikitable"
{| class="wikitable"
|+RTC Registers
!MMU
!MMU
!Flat
!Flat
Line 1,233: Line 1,300:
!0
!0
|-
|-
|$D690
|$D660
|$F0:1660
|
|
|RW
|INT_PENDING
|Seconds
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D691
|$D664
|$F0:1664
|
|
|RW
|INT_POLARITY
|Seconds Alarm
| colspan="8" |Per-interrupt flags (24-bit)
|0
|-
| colspan="3" |10s digit
|$D668
| colspan="4" |1s digit
|$F0:1668
|
|INT_EDGE
| colspan="8" |Per-interrupt flags (24-bit)
|-
|-
|$D692
|$D66C
|$F0:166C
|
|
|RW
|INT_MASK
|Minutes
| colspan="8" |Per-interrupt flags (24-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$D693
|
|
|RW
| +0 & $01
|Minutes Alarm
|
|0
|INT_VKY_SOF
| colspan="3" |10s digit
| colspan="8" |Start of Frame interrupt (beginning of VSYNC)
| colspan="4" |1s digit
|-
|-
|$D694
|
|
|RW
| +0 & $02
|Hours
|
|AM/PM
|INT_VKY_SOL
|0
| colspan="8" |Start of Line interrupt
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|-
|$D695
|
|
|RW
| +0 & $04
|Hours Alarm
|
|AM/PM
|INT_PS2_KBD
|0
| colspan="8" |PS/2 keyboard event
| colspan="2" |10s digit
|-
| colspan="4" |1s digit
|
| +0 & $08
|
|INT_PS2_MOUSE
| colspan="8" |PS/2 mouse event
|-
|-
|$D696
|
|
|RW
| +0 & $10
|Days
|
|0
|INT_TIMER_0
|0
| colspan="8" |TIMER0 has reached its target value
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|-
|$D697
|
|
|RW
| +0 & $20
|Days Alarm
|
|0
|INT_TIMER_1
|0
| colspan="8" |TIMER1 has reached its target value
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|-
|$D698
|
|
|RW
| +0 & $80
|Day of Week
|
|0
|INT_CARTRIDGE
|0
| colspan="8" |Interrupt asserted from cartridge port
|0
|0
|0
| colspan="3" |1s digit
|-
|-
|$D699
|
|
|RW
|
|Month
|
|0
|
|0
| colspan="8" |
|0
|10s digit
| colspan="4" |1s digit
|-
|-
|$D69A
|
|
|RW
| +1 & $01
|Year
|
| colspan="4" |10s digit
|INT_UART
| colspan="4" |1s digit
| colspan="8" |The UART is ready to receive or send data
|-
|-
|$D69B
|
|
|RW
| +1 & $10
|Rates
|
|0
|INT_RTC
| colspan="3" |WD
| colspan="8" |Interrupt from real time clock chip
| colspan="4" |RS
|-
|
| +1 & $20
|
|INT_VIA0
| colspan="8" |Event from the joystick VIA chip
|-
|-
|$D69C
|
|
|RW
| +1 & $40
|Enables
|
|0
|INT_VIA1
|0
| colspan="8" |Event from the keyboard VIA chip (F256k Series Only!)
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|-
|$D69D
|
|
|RW
| +1 & $80
|Flags
|
|0
|INT_SDC_INS
|0
| colspan="8" |SD Card has been inserted
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|-
|$D69E
|
|
|RW
|
|Control
|
|0
|
|0
| colspan="8" |
|0
|-
|0
|
|UTI
| +2 & $01
|STOP
|
|12/24
|IEC_DATA_i
|DSE
| colspan="8" |IEC data in
|-
|
| +2 & $02
|
|IEC_CLK_i
| colspan="8" |IEC clock in
|-
|
| +2 & $04
|
|IEC_ATN_i
| colspan="8" |IEC attention in
|-
|-
|$D69F
|
|
|RW
| +2 & $08
|Century
|
| colspan="4" |10s digit
|IEC_SREQ_i
| colspan="4" |1s digit
| colspan="8" |IEC service request in
|}
|}
====== $D670: DIP Switches ======
Main page: [[DIP switches]]
{| class="wikitable"
{| class="wikitable"
|+Text mode CLUT
!MMU
!MMU
!Flat
!Flat
Line 1,398: Line 1,449:
!0
!0
|-
|-
|$D800 - $D83F
|$D670
|$F0:1670
|R
|
|
|W
|GAMMA
|
|USER2
| colspan="8" |Text foreground colors (16 × BGRx)
|USER1
|-
|USER0
|$D840 - $D87F
| colspan="4" |BOOT
|
|W
|
| colspan="8" |Text background colors (16 × BGRx)
|}
|}
====== $D680: IEC ======
{| class="wikitable"
{| class="wikitable"
|+Integer Math Coprocessor
!MMU
!MMU
!Flat
!Flat
Line 1,425: Line 1,475:
!0
!0
|-
|-
|$DE00 - $DE01
|$D680
|
|$F0:1680
|RW
|R
|MULU_A
|IEC_I
| colspan="8" |Multiplication A (Unsigned 16-bit)
|SRQ_i
|—
|—
|ATN_i
|—
|—
|CLK_i
|DAT_i
|-
|-
|$DE00 - $DE02
|$D681
|
|$F0:1681
|RW
|RW
|MULU_B
|IEC_O
| colspan="8" |Multiplication B (Unsigned 16-bit)
|SRQ_o
|-
|RST_o
|$DE04 - $DE05
|NMI_EN
|
|ATN_o
|RW
|—
|DIVU_DEN
|—
| colspan="8" |Division Denominator (Unsigned 16-bit)
|CLK_o
|DAT_o
|}
 
====== $D690: RTC ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|-
|$DE06 - $DE07
|$D690
|
|$F0:1690
|RW
|RW
|DIVU_NUM
|Seconds
| colspan="8" |Division Numerator (Unsigned 16-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$DE08 - $DE0B
|$D691
|
|$F0:1691
|RW
|RW
|ADD_A
|Seconds Alarm
| colspan="8" |Addition A (Unsigned 32-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$DE0C - $DE0F
|$D692
|
|$F0:1692
|RW
|RW
|ADD_B
|Minutes
| colspan="8" |Addition B (Unsigned 32-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|
|$D693
|
|$F0:1693
|
|
| colspan="8" |
|-
|$DE10 - $DE13
|
|RW
|RW
|MULU
|Minutes Alarm
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|0
| colspan="3" |10s digit
| colspan="4" |1s digit
|-
|-
|$DE14 - $DE15
|$D694
|
|$F0:1694
|RW
|RW
|QUOU
|Hours
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|-
|$DE16 - $DE17
|$D695
|
|$F0:1695
|RW
|RW
|REMU
|Hours Alarm
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|AM/PM
|0
| colspan="2" |10s digit
| colspan="4" |1s digit
|-
|-
|$DE18 - $DE1B
|$D696
|
|$F0:1696
|RW
|RW
|ADD_R
|Days
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|0
|}
|0
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.
| colspan="2" |10s digit
 
| colspan="4" |1s digit
== IO Page 1 ==
|-
{| class="wikitable"
|$D697
|+Text Mode Font Sets
|$F0:1697
!MMU
|RW
!Flat
|Days Alarm
!R/W
|0
!Name
|0
!Description
| colspan="2" |10s digit
|-
| colspan="4" |1s digit
|$C000 - $C7FF
|-
|$F0:2000 - $F0:27FF
|$D698
|
|$F0:1698
|
|RW
|Font set 0 (256 × 8-byte chars)
|Day of Week
|-
|0
|$C800 - $CFFF
|0
|$F0:2800 - $F0:2FFF
|0
|
|0
|
|0
|Font set 1 (256 × 8-byte chars)
| colspan="3" |1s digit
|}
|-
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.
|$D699
{| class="wikitable"
|$F0:1699
|+Graphics CLUTS
|RW
!MMU
|Month
!Flat
|0
!R/W
|0
!Name
|0
!Description
|10s digit
|-
| colspan="4" |1s digit
|$D000 - $D3FF
|-
|$F0:3000 - $F0:33FF
|$D69A
|
|$F0:169A
|
|RW
|Graphics CLUT 0 (256 × BGRx)
|Year
|-
| colspan="4" |10s digit
|$D400 - $D7FF
| colspan="4" |1s digit
|$F0:3400 - $F0:37FF
|-
|
|$D69B
|
|$F0:169B
|Graphics CLUT 1 (256 × BGRx)
|RW
|Rates
|0
| colspan="3" |WD
| colspan="4" |RS
|-
|$D69C
|$F0:169C
|RW
|Enables
|0
|0
|0
|0
|AIE
|PIE
|PWRIE
|ABE
|-
|$D69D
|$F0:169D
|RW
|Flags
|0
|0
|0
|0
|AF
|PF
|PWRF
|BVF
|-
|$D69E
|$F0:169E
|RW
|Control
|0
|0
|0
|0
|UTI
|STOP
|12/24
|DSE
|-
|$D69F
|$F0:169F
|RW
|Century
| colspan="4" |10s digit
| colspan="4" |1s digit
|}
 
====== $D6A0: System Control Registers ======
Main page: [[Use the LEDs]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A0
|$F0:16A0
|W
|SYS0
|RESET
|NET_LED
|LOCK_LED
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|
|
|R
|SYS0
|—
|SD_WP
|SD_CD
|BUZZ
|L1
|L0
|SD_LED
|PWR_LED
|-
|$D6A1
|$F0:16A1
|RW
|SYS1
| colspan="2" |L1_RATE
| colspan="2" |L0_RATE
|SID_ST
|PSG_ST
|L1_MAN
|L0_MAN
|-
|$D6A2
|$F0:16A2
|RW
|RST0
| colspan="8" |Set to $DE to enable RESET bit
|-
|$D6A3
|$F0:16A3
|RW
|RST1
| colspan="8" |Set to $AD to enable RESET bit
|}
To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.
 
====== $D6A7: F256k Series LEDs ======
'''<span style="color:red>NOTE:</span>''' These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!
 
Main page: [[Use the LEDs#LED_Color_Registers_on_the_K_and_K2]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|W
|
| colspan="8" |Power LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AA
|$F0:16AA
|W
|
| colspan="8" |Media LED color ([[IO Pages#BGR|BGR]])
|-
|$D6AD
|$F0:16AD
|W
|
| colspan="8" |Shift LED color ([[IO Pages#BGR|BGR]])
|-
|$D6B3
|$F0:16B3
|W
|
| colspan="8" |Network LED color '''([[IO Pages#RGB|RGB]])'''
|}
 
====== $D6A7: Machine ID and FPGA Core Versions ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6A7
|$F0:16A7
|R
|MID
|—
|—
|—
| colspan="5" |[[MID codes for machine identification|Machine ID]]
|-
|$D6A8
|$F0:16A8
|R
|PCBID0
| colspan="8" |ASCII character 0: "B" (See also $D6EB)
|-
|$D6A9
|$F0:16A9
|R
|PCBID1
| colspan="8" |ASCII character 1: "0"
|-
|$D6AA
|$F0:16AA
|R
|CHSV
| colspan="8" |VICKY sub-version in BCD (16-bit)
|-
|$D6AC
|$F0:16AC
|R
|CHV
| colspan="8" |VICKY version in BCD (16-bit)
|-
|$D6AE
|$F0:16AE
|R
|CHN
| colspan="8" |VICKY number in BCD (16-bit)
|}
 
====== $D6E0: Mouse Pointer Control ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6E0
|$F0:16E0
|W
|
|—
|—
|—
|—
|—
|—
|MODE
|EN
|-
|$D6E2
|$F0:16E2
|RW
|
| colspan="8" |X (16-bit)
|-
|$D6E4
|$F0:16E4
|RW
|
| colspan="8" |Y (16-bit)
|-
|$D6E6
|$F0:16E6
|W
|
| colspan="8" |PS2_BYTE_0
|-
|$D6E7
|$F0:16E7
|W
|
| colspan="8" |PS2_BYTE_1
|-
|$D6E8
|$F0:16E8
|W
|
| colspan="8" |PS2_BYTE_2
|}
 
====== $D6EB: PCB Information ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D6EB
|$F0:16EB
|R
|PCBMA
| colspan="8" |PCB Major Rev (ASCII)
|-
|$D6EC
|$F0:16EC
|R
|PCBMI
| colspan="8" |PCB Minor Rev (ASCII)
|-
|$D6ED
|$F0:16ED
|R
|PCBD
| colspan="8" |PCB Day (BCD)
|-
|$D6EE
|$F0:16EE
|R
|PCBM
| colspan="8" |PCB Month (BCD)
|-
|$D6EF
|$F0:16EF
|R
|PCBY
| colspan="8" |PCB Year (BCD)
|}
 
===== $D700: VS1053b (F256 Gen 2 only) =====
Main page: [[Use the VS1053b chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D700
|$F0:1700
|
|SCI Control
| colspan="8" |Control the flow of information
|-
|$D701
|$F0:1701
|
|SCI Address
| colspan="8" |Select to which VS1053b address to write to
|-
|$D702
|$F0:1702
|
|SCI Data 1
| colspan="8" |First byte of data
|-
|$D703
|$F0:1703
|
|SCI Data 2
| colspan="8" |Second byte of data
|-
|$D704
|$F0:1704
|
|FIFO Count 1
| colspan="8" |First byte of the remaining byte count in the FIFO
|-
|$D705
|$F0:1705
|
|FIFO Count 2
| colspan="8" |Second byte of the remaining byte count in the FIFO
|}
If the MIDI mode is set up, its data port is down at [[IO Pages#$DDB1: VS1053b MIDI (F256 Gen 2 only)|$DDB1]].
 
===== $D800: Text Mode CLUT =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D800 - $D83F
|$F0:1800 - $F0:183F
|W
|
| colspan="8" |Text foreground colors (16 × [[IO Pages#BGRx|BGRx]])
|-
|$D840 - $D87F
|$F0:1840 - $F0:187f
|W
|
| colspan="8" |Text background colors (16 × [[IO Pages#BGRx|BGRx]])
|}
 
===== $D880: NES/SNES Gamepads =====
Main page: [[Use the SNES/NES controllers]]
 
Buttons are active low, 0 = pressed
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D880
|$F0:1880
|R
|NES_CTRL
|NES_TRIG
|DONE
|—
|—
|—
|MODE
|—
|NES_EN
|-
|
|
|W
|NES_CTRL
|NES_TRIG
|—
|—
|—
|—
|MODE
|—
|NES_EN
|-
|$D884
|$F0:1884
|
|
| colspan="8" |Pad 0
|-
|$D886
|$F0:1886
|
|
| colspan="8" |Pad 1
|-
|$D888
|$F0:1888
|
|
| colspan="8" |Pad 2
|-
|$D88A
|$F0:188A
|
|
| colspan="8" |Pad 3
|-
|
| +0
|
|Mode=0
|A
|B
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +0
|
|Mode=1
|B
|Y
|SELECT
|START
|UP
|DOWN
|LEFT
|RIGHT
|-
|
| +1
|
|Mode=1
|—
|—
|—
|—
|A
|X
|L
|R
|}
 
===== $D900: Sprites =====
Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in [[Memory Management|MMU_IO_CONTROL]] at $0001.
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$D900 - $DAFF
|$F0:1900 - $F0:1AFF
|
|
| colspan="8" |64 × 8-byte Sprite Registers
|-
|
| +0
|W
|
|—
| colspan="2" |SIZE
| colspan="2" |LAYER
| colspan="2" |LUT
|ENABLE
|-
|
|
|
|SIZE
| colspan="8" |0: 32×32
1: 24×24
 
2: 16×16
 
3: 8×8
|-
|
| +1
|W
|
| colspan="8" |[[IO Pages#SRAM Address|SRAM Address]] of sprite pixels (24-bit)
|-
|
| +4
|W
|
| colspan="8" |X position (16-bit)
|-
|
| +6
|W
|
| colspan="8" |Y position (16-bit)
|}
 
===== $DB00: Moar system =====
 
====== $DB00: VIAs ======
See: [[Keyboard raw codes]]
 
<nowiki>*</nowiki> = F256k series only
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DB00*
|$F0:1B00*
|
|VIA1
| colspan="8" |Internal Keyboard VIA*
|-
|$DC00
|$F0:1C00
|
|VIA0
| colspan="8" |Atari joystick VIA
|-
|
| +0
|RW
|IORB
| colspan="8" |Port B Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 0, keyboard column 8*
VIA1: Keyboard columns 0-7*
|-
|
| +1
|RW
|IORA
| colspan="8" |Port A Data
|-
|
|
|
|
| colspan="8" |VIA0: Joystick 1
VIA1: Keyboard row*
|-
|
| +2
|RW
|DDRB
| colspan="8" |Port B Data Direction Register
|-
|
| +3
|RW
|DDRA
| colspan="8" |Port A Data Direction Register
|-
|
| +4
|RW
|T1C
| colspan="8" |Timer 1 Counter (16-bit)
|-
|
| +6
|RW
|T1L
| colspan="8" |Timer 1 Latch (16-bit)
|-
|
| +8
|RW
|T2C
| colspan="8" |Timer 2 Counter (16-bit)
|-
|
| +A
|RW
|SDR
| colspan="8" |Serial Data Registers
|-
|
| +B
|RW
|ACR
| colspan="2" |T1_CTRL
|T2_CTRL
| colspan="3" |SR_CTRL
|PBL_EN
|PAL_EN
|-
|
| +C
|RW
|PCR
| colspan="3" |CB2_CTRL
|CB1_CTRL
| colspan="3" |CA1_CTRL
|CA1_CTRL
|-
|
| +D
|RW
|IFR
|IRQF
|T1F
|T2F
|CB1F
|CB2F
|SRF
|CA1F
|CA2F
|-
|
| +E
|RW
|IER
|SET
|T1E
|T2E
|CB1E
|CB2E
|SRE
|CA1E
|CA2E
|-
|
| +F
|RW
|IORA2
| colspan="8" |Port A Data (no handshake)
|}
{| class="wikitable"
|+VIA0 Joystick Bits
!7
!6
!5
!4
!3
!2
!1
!0
|-
|Keyboard column 8*
|Button 2
|Button 1
|Button 0
|Right
|Left
|Down
|Up
|}
{| class="wikitable"
|+VIA1 Internal Keyboard Matrix*
!
!PB0
!PB1
!PB2
!PB3
!PB4
!PB5
!PB6
!PB7
!VIA0 PB7
|-
|'''PA0'''
|Del
|Return
|Left
|F7
|F1
|F3
|F5
|Up
|Down
|-
|'''PA1'''
|3
|W
|A
|4
|Z
|S
|E
|LShift
|
|-
|'''PA2'''
|5
|R
|D
|6
|C
|F
|T
|X
|
|-
|'''PA3'''
|7
|Y
|G
|8
|B
|H
|U
|V
|
|-
|'''PA4'''
|9
|I
|J
|0
|M
|K
|O
|N
|
|-
|'''PA5'''
| -
|P
|L
|Caps
|.
|;
|[
|,
|
|-
|'''PA6'''
|=
|]
|'
|Home
|RShift
|Alt
|Tab
|/
|Right
|-
|'''PA7'''
|1
|BS
|Ctrl
|2
|Space
|Foenix
|Q
|Run/Stop
|
|}
 
====== $DD00: SD Card Controllers ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD00
|$F0:1D00
|
|
| colspan="8" |SD Card 0 (external)
|-
|$DD20
|$F0:1D20
|
|
| colspan="8" |SD Card 1 (internal)
|-
|
| +0
|RW
|
|SPI_BUSY
|—
|—
|—
|—
|—
|SPI_CLK
|CS_EN
|-
|
| +1
|RW
|
| colspan="8" |SPI_DATA
|}
'''SPI_CLK''': 400MHz init clock when set, 12.5MHz standard clock when clear.
 
====== $DD40: F256K2 Case LCD Screen ======
Main page: [[Use the K2 LCD]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DD40
|$F0:1D40
|
|LCD_CMD_CMD
| colspan="8" |Command
|-
|$DD41
|$F0:1D41
|
|LCD_CMD_DTA
| colspan="8" |Data
|-
|$DD42
|$F0:1D42
|
|LCD_PIX_LO
| colspan="3" |Green[2:0]
| colspan="5" |Blue
|-
|$DD43
|$F0:1D43
|
|LCD_PIX_HI
| colspan="5" |Red
| colspan="3" |Green[5:3]
|}
 
===== $DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only) =====
Main page: [[Use the Sam2695 Dream MIDI chip]]
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDA0
|$F0:1DA0
|R
|MIDI_STATUS
|TX_EMPTY
|RX_FULL
|—
|—
|—
|—
|—
|—
|-
|$DDA1
|$F0:1DA1
|RW
|MIDI_FIFO_DATA_PORT
| colspan="8" |Data
|-
|$DDA2
|$F0:1DA2
|
|MIDI_RXD_COUNT
| colspan="8" |Rx FIFO Data count (12-bit)
|-
|$DDA4
|$F0:1DA4
|
|MIDI_TXD_COUNT
| colspan="8" |
|}
The SAM2695 drives the hardware MIDI jacks.
 
Writing to $DDA1 also gets written to the wavetable pin headers.
 
===== $DDB1: VS1053b MIDI Port (F256 Gen 2 only) =====
The rest of the VS1053b is up at [[IO Pages#$D700: VS1053b (F256 Gen 2 only)|$D700]].
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDB1
|$F0:1DB1
|W
|
| colspan="8" |Data
|}
 
===== $DDC0: Optical Keyboard Controller (F256K2 Only) =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DDC0
|$F0:1DC0
|
|OPT_KBD_DATA
| colspan="8" |FIFO queue. Each event is two 8-bit reads from here
|-
|$DDC1
|$F0:1DC1
|R
|OPT_KBD_STATUS
|MECH
|—
|—
|—
|—
|—
|—
|FIFO_EMPTY
|-
|
|
|
|
| colspan="8" |MECH = No optical keyboard if set
|-
|$DDC2
|$F0:1DC2
|
|OPT_KB_COUNT
| colspan="8" |Number of events in optical keyboard queue (12-bit)
|}
Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:
{| class="wikitable"
|+Event Data
!Byte
!7
!6
!5
!4
!3
!2
!1
!0
|-
|0
| colspan="4" |Row number (0-7)
|—
|—
|—
|Col8
|-
|1
|Col7
|Col6
|Col5
|Col4
|Col3
|Col2
|Col1
|Col0
|}
 
===== $DE00: Integer Math Coprocessor =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DE00
|$F0:1E00
|RW
|MULU_A
| colspan="8" |Multiplication A (Unsigned 16-bit)
|-
|$DE02
|$F0:1E02
|RW
|MULU_B
| colspan="8" |Multiplication B (Unsigned 16-bit)
|-
|$DE04
|$F0:1E04
|RW
|DIVU_DEN
| colspan="8" |Division Denominator (Unsigned 16-bit)
|-
|$DE06
|$F0:1E06
|RW
|DIVU_NUM
| colspan="8" |Division Numerator (Unsigned 16-bit)
|-
|$DE08
|$F0:1E08
|RW
|ADD_A
| colspan="8" |Addition A (Unsigned 32-bit)
|-
|$DE0C
|$F0:1E0C
|RW
|ADD_B
| colspan="8" |Addition B (Unsigned 32-bit)
|-
|
|
|
|
| colspan="8" |
|-
|$DE10
|$F0:1E10
|RW
|MULU
| colspan="8" |Multiplication A×B Result (Unsigned 32-bit)
|-
|$DE14
|$F0:1E14
|RW
|QUOU
| colspan="8" |Quotient of Num/Den (Unsigned 16-bit)
|-
|$DE16
|$F0:1E16
|RW
|REMU
| colspan="8" |Remainder of Num/Den (Unsigned 16-bit)
|-
|$DE18
|$F0:1E18
|RW
|ADD_R
| colspan="8" |Addition A+B Result (Unsigned 32-bit)
|}
Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.
 
===== $DF00: DMA Controller =====
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!7
!6
!5
!4
!3
!2
!1
!0
|-
|$DF00
|$F0:1F00
|RW
|
|START
|—
|—
|—
|INT_EN
|FILL
|2D
|ENABLE
|-
|$DF01
|$F0:1F01
|W
|
| colspan="8" |Fill data byte
|-
|
|
|R
|
|BUSY
|—
|—
|—
|—
|—
|—
|—
|-
|$DF04
|$F0:1F04
|RW
|
| colspan="8" |Source [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF08
|$F0:1F08
|RW
|
| colspan="8" |Destination [[IO Pages#SRAM Address|SRAM Address]] (24-bit)
|-
|$DF0C
|$F0:1F0C
|RW
|
| colspan="8" |Count (24-bit, not 2D mode)
|-
|
|
|RW
|
| colspan="8" |Width (16-bit, 2D mode)
|-
|$DF0E
|$F0:1F0E
|RW
|
| colspan="8" |Height (16-bit, 2D mode)
|-
|$DF10
|$F0:1F10
|RW
|
| colspan="8" |Source stride (16-bit, 2D mode)
|-
|$DF12
|$F0:1F12
|RW
|
| colspan="8" |Destination stride (16-bit, 2D mode)
|}
DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.
 
== IO Page 1 ==
 
====== $C000: Text Mode Font Sets ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$C000 - $C7FF
|$F0:2000 - $F0:27FF
|RW
|
|Font set 0 (256 × 8-byte chars)
|-
|$C800 - $CFFF
|$F0:2800 - $F0:2FFF
|RW
|
|Font set 1 (256 × 8-byte chars)
|}
Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.
 
====== $D000: Graphics CLUTs ======
{| class="wikitable"
!MMU
!Flat
!R/W
!Name
!Description
|-
|$D000 - $D3FF
|$F0:3000 - $F0:33FF
|RW
|
|Graphics CLUT 0 (256 × [[IO Pages#BGRx|BGRx]])
|-
|$D400 - $D7FF
|$F0:3400 - $F0:37FF
|RW
|
|Graphics CLUT 1 (256 × [[IO Pages#BGRx|BGRx]])
|-
|-
|$D800 - $DBFF
|$D800 - $DBFF
|$F0:3800 - $F0:3BFF
|$F0:3800 - $F0:3BFF
|RW
|
|
|
|Graphics CLUT 2 (256 × [[IO Pages#BGRx|BGRx]])
|Graphics CLUT 2 (256 × BGRx)
|-
|-
|$DC00 - $DFFF
|$DC00 - $DFFF
|$F0:3C00 - $F0:3FFF
|$F0:3C00 - $F0:3FFF
|RW
|
|
|
|Graphics CLUT 3 (256 × [[IO Pages#BGRx|BGRx]])
|Graphics CLUT 3 (256 × BGRx)
|}
|}
The 4th byte ('x') in each entry is unused.
== IO Page 2 ==


== IO Page 2 ==
====== $C000: Text Screen Character Matrix ======
{| class="wikitable"
{| class="wikitable"
|+
!MMU
!MMU
!Flat
!Flat
Line 1,567: Line 2,948:


80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.
{| class="wikitable"
|+Size of matrix
!Rows
!40 column
!80 column
|-
|25
|1000, $03E8
|2000, $07D0
|-
|30
|1200, $04B0
|2400, $0960
|-
|50
|2000, $07D0
|4000, $0FA0
|-
|60
|2400, $0960
|4800, $12C0
|}


== IO Page 3 ==
== IO Page 3 ==
====== $C000: Text Screen Color Matrix ======
{| class="wikitable"
{| class="wikitable"
|+
!MMU
!MMU
!Flat
!Flat

Latest revision as of 18:52, 25 February 2026

More detailed information is found in the Manuals.

Notes

SRAM Address: Raw addresses for the system SRAM chip. The VICKY can only address the system SRAM (for now, DDR3 support coming). The 1st gen hardware has 512kB (19-bit space), while the 2nd gen has 2MB (21-bit space). The 24-bit pointers used are direct addresses into the SRAM chip, regardless of how the 2MB is mapped to the CPU's/MMU's address space. For instance, the Core2x MMU has 4 separate 512kB banks at non-consecutive addresses; these 4 banks are all linear+consecutive in the SRAM, and that view must be addressed here instead of its 8k block offset addresses.

Model names: Certain features are only available on certain models, and these terms are used exactly. For instance, "F256Jr" means exactly the 1st gen Jr, not the entire Jr line.

BGR: A 3-byte color entry in Blue, Green, Red order.

BGRx: A 4-byte aligned color entry in Blue, Green, Red order, with the 4th byte unused.

RGB: A 3-byte color entry in Red, Green, Blue order, as things should be.

IO Page 0

$C000: Gamma Lookup
MMU Flat R/W Name Description
$C000 - $C0FF $F0:0000 - $F0:00FF RW Blue gamma conversion table
$C400 - $C4FF $F0:0400 - $F0:04FF RW Green gamma conversion table
$C800 - $C8FF $F0:0800 - $F0:08FF RW Red gamma conversion table

Each area is 256 bytes, mapping an 8-bit value (offset) to an 8-bit value (memory value), mirrored 4 times currently to fill each 1kB address space.

$CC00: Mouse Pointer Bitmap

See: Use the PS/2 Mouse

MMU Flat R/W Name Description
$CC00 - $CCFF $F0:0C00 - $F0:0CFF RW Mouse pointer bitmap (16×16 greyscale bytes)

This is currently mirrored 4 times in $CC00 - $CFFF.

$D000: VICKY Config
$D000: Master Control Registers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D000 $F0:1000 RW MSTR_CTRL_0 — GAMMA SPRITE TILE BITMAP GRAPH OVRLY TEXT
$D001 $F0:1001 RW MSTR_CTRL_1 — — FON_SET FON_OVLY MON_SLP DBL_Y DBL_X CLK_70

TEXT: Enable text layer

OVRLY: Overlay text on graphics, by making text background transparent. See FON_OVLY

GRAPH: Enable graphics layers (tile, sprites, bitmaps)

BITMAP: Enable bitmap layers (if GRAPH is also set)

TILE: Enable tile layers (if GRAPH is also set)

SPRITE: Enable sprite layers (if GRAPH is also set)

GAMMA: Enable gamma correction

CLK_70: Enable 400p70, else 480p60

DBL_X, DBL_Y: Double text mode character width & height

MON_SLP: Turn off monitor SYNC, putting it into sleep mode

FON_OVLY: Only BG color 0 is transparent in OVRLY mode. Else, all BG colors are transparent.

FON_SET: Chooses font set 0 or 1

$D002: Layers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D002 $F0:1002 RW — Layer 1 — Layer 0
$D003 $F0:1003 RW — — — — — Layer 2
Values 0-2: Bitmap 0-2

4-6: Tilemap 0-2

$D004: Border
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D004 $F0:1004 RW BRDR_CTRL — SCROLL_X — — — ENABLE
$D005 $F0:1005 RW BRDR_BLUE Border color Blue component
$D006 $F0:1006 RW BRDR_GREEN Border color Green component
$D007 $F0:1007 RW BRDR_RED Border color Red component
$D008 $F0:1008 RW BRDR_WIDTH — — — SIZE_X
$D009 $F0:1009 RW BRDR_HEIGHT — — — SIZE_Y
$D00D: Background
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D00D $F0:100D RW BGND_BLUE Background color Blue component
$D00E $F0:100E RW BGND_GREEN Background color Green component
$D00F $F0:100F RW BGND_RED Background color Red component
$D010: Text Cursor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D010 $F0:1010 RW CCR — — — — FLASH_DIS RATE ENABLE
RATE 0: 1 second

1: 1/2 second 2: 1/4 second 3: 1/8 second

$D012 $F0:1012 RW CCH Cursor character code
$D014 $F0:1014 RW CURX Cursor X position (16-bit)
$D016 $F0:1016 RW CURY Cursor Y position (16-bit)
$D018: Raster
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D018 $F0:1018 R RAST_COL Raster current column (12-bit)
$D01A $F0:101A R RAST_ROW Raster current row (12-bit)
$D018 $F0:1018 W LINT_CTRL — — — — — — — ENABLE
$D019 $F0:1019 W LINT_L Line interrupt line (12-bit)
Raster line numbers in a frame
Dec Hex Description
0 $000 Start of frame, VBLANK, and non-Core2x DMA
2 $002 Core2x: DMA starts halfway through line (8192 SRAM cycles safety margin from SOF)
43 $02B DMA safety margin, pauses from here
45 $02D First visible line
524 $20C Last visible line, last line of frame
$D100: Bitmaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D100 $F0:1100 Bitmap 0
$D108 $F0:1108 Bitmap 1
$D110 $F0:1110 Bitmap 2
+0 RW — — — — — CLUT ENABLE
+1 RW SRAM Address of pixels (24-bit)
$D200: Tilemaps
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D200 $F0:1200 Tilemap 0
$D20C $F0:120C Tilemap 1
$D218 $F0:1218 Tilemap 2
+$00 W — — — TILE_SIZE_8 — — — ENABLE
+$01 W SRAM Address of tile map entries (24-bit) **
+$04 W MAP_SIZE_X (8-bit)
+$06 W MAP_SIZE_Y (8-bit)
+$08 W Tile Scroll X[3:0] 16x16 Pixel Scroll SSX
— 8x8 SSX
+$09 W — — Tile Scroll X[9:4]
+$0A W Tile Scroll Y[3:0] 16x16 Pixel Scroll SSY
— 8x8 SSY
+$0B W — — — — Tile Scroll Y[7:4]

** = In some configurations, the first tilemap entry is ignored and the map starts at the second entry. This is still being investigated.

The scroll registers state where to start drawing the tilemap, meaning they scroll up and to the left as they increase.

Tile Map Entry
Offset 7 6 5 4 3 2 1 0
+0 Tile number
+1 — — — CLUT Tileset
$D280: Tilesets
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D280 $F0:1280 Tileset 0
$D284 $F0:1284 Tileset 1
$D288 $F0:1288 Tileset 2
$D28C $F0:128C Tileset 3
$D290 $F0:1290 Tileset 4
$D294 $F0:1294 Tileset 5
$D298 $F0:1298 Tileset 6
$D29C $F0:129C Tileset 7
+0 W SRAM Address of tile pixels (24-bit)
+3 W — — — — SQUARE — — —
Layout of Tileset Pixels
SQUARE 8×8 px Tiles 16×16 px Tiles
0 8×1024 px 16×2048 px
1 128×128 px 256×256 px
$D400: Sound
$D400: SID chips

Stereo separation is enabled with the SID_ST flag. By default, both PSGs go to both speakers.

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D400 $F0:1400 Left SID
$D500 $F0:1500 Right SID
+$00 W Voice 1 Frequency (16-bit)
+$02 W Pulse width (12-bit)
+$04 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$05 W ATTACK DELAY
+$06 W SUSTAIN RELEASE
+$07 W Voice 2 Frequency (16-bit)
+$09 W Pulse width (12-bit)
+$0B W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$0C W ATTACK DELAY
+$0D W SUSTAIN RELEASE
+$0E W Voice 3 Frequency (16-bit)
+$10 W Pulse width (12-bit)
+$12 W NOISE PULSE SAW TRI TEST RING SYNC GATE
+$13 W ATTACK DELAY
+$14 W SUSTAIN RELEASE
+$15 W Misc — — — — — FC[2:0]
+$16 W FC[10:3]
+$17 W RESONANCE EXT FILTV3 FILTV2 FILTV1
+$18 W MUTEV3 HIGH BAND LOW VOLUME
$D580: OPL3 (NOT on F256Jr!)

Main page: Use the OPL3 YMF262

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D580 $F0:1580 W Address registers for ports $000 - $0FF
$D581 $F0:1581 W Data registers for all ports
$D582 $F0:1582 W Address register for ports $100 - $1FF
$D600: PSGs

Main page: Use the PSG

Stereo separation is enabled with the PSG_ST flag. By default, both PSGs go to both speakers.

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D600 $F0:1600 PSG Left
$D608 $F0:1608 PSG Left + Right
$D610 $F0:1610 PSG Right
$D620: CODEC

Main page: Use the CODEC

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D620 $F0:1620 W DATA[7:0]
$D621 $F0:1621 W REGISTER DATA[8]
$D622 $F0:1622 R — — — — — — — BUSY
W — — — — — — — START
$D630: System
$D630: UART
MMU Flat R/W Name 7 6 5 4 3 2 1 0
DLAB = 0
$D630 $F0:1630 R RXD RX_DATA
W TXR TX_DATA
$D631 $F0:1631 RW IER — — — — STAT ERR TXE RXA
DLAB = 1
$D630 $F0:1630 RW DL DIV (16-bit)
$D632 $F0:1632 R IIR FIFO FIFO64 — STATE /PENDING
W FCR RXT FIFO64 — DMA TXR RXR FIFOE
$D633 $F0:1633 RW LCR DLAB — PARITY STOP DATA
$D640: PS/2

See: Use the PS/2 Mouse

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D640 $F0:1640 RW PS2_CTRL — — MCLR KCLR M_WR — K_WR —
$D641 $F0:1641 RW PS2_OUT Data to keyboard
$D642 $F0:1642 R KBD_IN Data in from keyboard FIFO
$D643 $F0:1643 R MS_IN Data in from mouse FIFO
$D644 $F0:1644 R PS2_STAT K_AK K_NK M_AK M_NK — — MEMP KEMP
$D650: Interval Timers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D650 $F0:1650 W T0_CTR — — — — UP LD CLR EN
R T0_STAT — — — — — — — EQ
$D651 $F0:1651 RW T0_VAL VAL (24-bit)
$D654 $F0:1654 RW T0_CMP_CTR — — — — — — RELD RECLR
$D655 $F0:1655 RW T0_CMP CMP (24-bit)
$D658 $F0:1658 W T1_CTR — — — — UP LD CLR EN
R T1_STAT — — — — — — — EQ
$D659 $F0:1659 RW T1_VAL VAL (24-bit)
$D65C $F0:165C RW T1_CMP_CTR — — — — — — RELD RECLR
$D65D $F0:165D RW T1_CMP CMP (24-bit)

WARNING: The 24-bit timer values are not latched and will continue to update between both reads and writes of individual bytes if it stays enabled!

Timer 0 runs at the 25.175MHz dot clock, while timer 1 counts frames which will be 60Hz or 70Hz depending on the video mode.

$D660: Interrupts

Main page: IRQ, IRQ Programming

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D660 $F0:1660 INT_PENDING Per-interrupt flags (24-bit)
$D664 $F0:1664 INT_POLARITY Per-interrupt flags (24-bit)
$D668 $F0:1668 INT_EDGE Per-interrupt flags (24-bit)
$D66C $F0:166C INT_MASK Per-interrupt flags (24-bit)
+0 & $01 INT_VKY_SOF Start of Frame interrupt (beginning of VSYNC)
+0 & $02 INT_VKY_SOL Start of Line interrupt
+0 & $04 INT_PS2_KBD PS/2 keyboard event
+0 & $08 INT_PS2_MOUSE PS/2 mouse event
+0 & $10 INT_TIMER_0 TIMER0 has reached its target value
+0 & $20 INT_TIMER_1 TIMER1 has reached its target value
+0 & $80 INT_CARTRIDGE Interrupt asserted from cartridge port
+1 & $01 INT_UART The UART is ready to receive or send data
+1 & $10 INT_RTC Interrupt from real time clock chip
+1 & $20 INT_VIA0 Event from the joystick VIA chip
+1 & $40 INT_VIA1 Event from the keyboard VIA chip (F256k Series Only!)
+1 & $80 INT_SDC_INS SD Card has been inserted
+2 & $01 IEC_DATA_i IEC data in
+2 & $02 IEC_CLK_i IEC clock in
+2 & $04 IEC_ATN_i IEC attention in
+2 & $08 IEC_SREQ_i IEC service request in
$D670: DIP Switches

Main page: DIP switches

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D670 $F0:1670 R GAMMA USER2 USER1 USER0 BOOT
$D680: IEC
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D680 $F0:1680 R IEC_I SRQ_i — — ATN_i — — CLK_i DAT_i
$D681 $F0:1681 RW IEC_O SRQ_o RST_o NMI_EN ATN_o — — CLK_o DAT_o
$D690: RTC
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D690 $F0:1690 RW Seconds 0 10s digit 1s digit
$D691 $F0:1691 RW Seconds Alarm 0 10s digit 1s digit
$D692 $F0:1692 RW Minutes 0 10s digit 1s digit
$D693 $F0:1693 RW Minutes Alarm 0 10s digit 1s digit
$D694 $F0:1694 RW Hours AM/PM 0 10s digit 1s digit
$D695 $F0:1695 RW Hours Alarm AM/PM 0 10s digit 1s digit
$D696 $F0:1696 RW Days 0 0 10s digit 1s digit
$D697 $F0:1697 RW Days Alarm 0 0 10s digit 1s digit
$D698 $F0:1698 RW Day of Week 0 0 0 0 0 1s digit
$D699 $F0:1699 RW Month 0 0 0 10s digit 1s digit
$D69A $F0:169A RW Year 10s digit 1s digit
$D69B $F0:169B RW Rates 0 WD RS
$D69C $F0:169C RW Enables 0 0 0 0 AIE PIE PWRIE ABE
$D69D $F0:169D RW Flags 0 0 0 0 AF PF PWRF BVF
$D69E $F0:169E RW Control 0 0 0 0 UTI STOP 12/24 DSE
$D69F $F0:169F RW Century 10s digit 1s digit
$D6A0: System Control Registers

Main page: Use the LEDs

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A0 $F0:16A0 W SYS0 RESET NET_LED LOCK_LED BUZZ L1 L0 SD_LED PWR_LED
R SYS0 — SD_WP SD_CD BUZZ L1 L0 SD_LED PWR_LED
$D6A1 $F0:16A1 RW SYS1 L1_RATE L0_RATE SID_ST PSG_ST L1_MAN L0_MAN
$D6A2 $F0:16A2 RW RST0 Set to $DE to enable RESET bit
$D6A3 $F0:16A3 RW RST1 Set to $AD to enable RESET bit

To trigger a software reset, write $DE and $AD to $D6A2 & 3 respectively (which is $ADDE in little-endian 16-bit write instead of $DEAD, but whatever), then set the RESET bit and clear it.

$D6A7: F256k Series LEDs

NOTE: These write-only addresses overlap with the read-only MID addresses! The network LED color is non-contiguous with the others, and swapped color order!

Main page: Use the LEDs#LED_Color_Registers_on_the_K_and_K2

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 W Power LED color (BGR)
$D6AA $F0:16AA W Media LED color (BGR)
$D6AD $F0:16AD W Shift LED color (BGR)
$D6B3 $F0:16B3 W Network LED color (RGB)
$D6A7: Machine ID and FPGA Core Versions
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6A7 $F0:16A7 R MID — — — Machine ID
$D6A8 $F0:16A8 R PCBID0 ASCII character 0: "B" (See also $D6EB)
$D6A9 $F0:16A9 R PCBID1 ASCII character 1: "0"
$D6AA $F0:16AA R CHSV VICKY sub-version in BCD (16-bit)
$D6AC $F0:16AC R CHV VICKY version in BCD (16-bit)
$D6AE $F0:16AE R CHN VICKY number in BCD (16-bit)
$D6E0: Mouse Pointer Control
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6E0 $F0:16E0 W — — — — — — MODE EN
$D6E2 $F0:16E2 RW X (16-bit)
$D6E4 $F0:16E4 RW Y (16-bit)
$D6E6 $F0:16E6 W PS2_BYTE_0
$D6E7 $F0:16E7 W PS2_BYTE_1
$D6E8 $F0:16E8 W PS2_BYTE_2
$D6EB: PCB Information
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D6EB $F0:16EB R PCBMA PCB Major Rev (ASCII)
$D6EC $F0:16EC R PCBMI PCB Minor Rev (ASCII)
$D6ED $F0:16ED R PCBD PCB Day (BCD)
$D6EE $F0:16EE R PCBM PCB Month (BCD)
$D6EF $F0:16EF R PCBY PCB Year (BCD)
$D700: VS1053b (F256 Gen 2 only)

Main page: Use the VS1053b chip

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D700 $F0:1700 SCI Control Control the flow of information
$D701 $F0:1701 SCI Address Select to which VS1053b address to write to
$D702 $F0:1702 SCI Data 1 First byte of data
$D703 $F0:1703 SCI Data 2 Second byte of data
$D704 $F0:1704 FIFO Count 1 First byte of the remaining byte count in the FIFO
$D705 $F0:1705 FIFO Count 2 Second byte of the remaining byte count in the FIFO

If the MIDI mode is set up, its data port is down at $DDB1.

$D800: Text Mode CLUT
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D800 - $D83F $F0:1800 - $F0:183F W Text foreground colors (16 × BGRx)
$D840 - $D87F $F0:1840 - $F0:187f W Text background colors (16 × BGRx)
$D880: NES/SNES Gamepads

Main page: Use the SNES/NES controllers

Buttons are active low, 0 = pressed

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D880 $F0:1880 R NES_CTRL NES_TRIG DONE — — — MODE — NES_EN
W NES_CTRL NES_TRIG — — — — MODE — NES_EN
$D884 $F0:1884 Pad 0
$D886 $F0:1886 Pad 1
$D888 $F0:1888 Pad 2
$D88A $F0:188A Pad 3
+0 Mode=0 A B SELECT START UP DOWN LEFT RIGHT
+0 Mode=1 B Y SELECT START UP DOWN LEFT RIGHT
+1 Mode=1 — — — — A X L R
$D900: Sprites

Core2x: There are 2 selectable banks of 64 sprites at these locations, depending on the bit 6 (SPR_SEL) in MMU_IO_CONTROL at $0001.

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$D900 - $DAFF $F0:1900 - $F0:1AFF 64 × 8-byte Sprite Registers
+0 W — SIZE LAYER LUT ENABLE
SIZE 0: 32×32

1: 24×24

2: 16×16

3: 8×8

+1 W SRAM Address of sprite pixels (24-bit)
+4 W X position (16-bit)
+6 W Y position (16-bit)
$DB00: Moar system
$DB00: VIAs

See: Keyboard raw codes

* = F256k series only

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DB00* $F0:1B00* VIA1 Internal Keyboard VIA*
$DC00 $F0:1C00 VIA0 Atari joystick VIA
+0 RW IORB Port B Data
VIA0: Joystick 0, keyboard column 8*

VIA1: Keyboard columns 0-7*

+1 RW IORA Port A Data
VIA0: Joystick 1

VIA1: Keyboard row*

+2 RW DDRB Port B Data Direction Register
+3 RW DDRA Port A Data Direction Register
+4 RW T1C Timer 1 Counter (16-bit)
+6 RW T1L Timer 1 Latch (16-bit)
+8 RW T2C Timer 2 Counter (16-bit)
+A RW SDR Serial Data Registers
+B RW ACR T1_CTRL T2_CTRL SR_CTRL PBL_EN PAL_EN
+C RW PCR CB2_CTRL CB1_CTRL CA1_CTRL CA1_CTRL
+D RW IFR IRQF T1F T2F CB1F CB2F SRF CA1F CA2F
+E RW IER SET T1E T2E CB1E CB2E SRE CA1E CA2E
+F RW IORA2 Port A Data (no handshake)
VIA0 Joystick Bits
7 6 5 4 3 2 1 0
Keyboard column 8* Button 2 Button 1 Button 0 Right Left Down Up
VIA1 Internal Keyboard Matrix*
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VIA0 PB7
PA0 Del Return Left F7 F1 F3 F5 Up Down
PA1 3 W A 4 Z S E LShift
PA2 5 R D 6 C F T X
PA3 7 Y G 8 B H U V
PA4 9 I J 0 M K O N
PA5 - P L Caps . ; [ ,
PA6 = ] ' Home RShift Alt Tab / Right
PA7 1 BS Ctrl 2 Space Foenix Q Run/Stop
$DD00: SD Card Controllers
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD00 $F0:1D00 SD Card 0 (external)
$DD20 $F0:1D20 SD Card 1 (internal)
+0 RW SPI_BUSY — — — — — SPI_CLK CS_EN
+1 RW SPI_DATA

SPI_CLK: 400MHz init clock when set, 12.5MHz standard clock when clear.

$DD40: F256K2 Case LCD Screen

Main page: Use the K2 LCD

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DD40 $F0:1D40 LCD_CMD_CMD Command
$DD41 $F0:1D41 LCD_CMD_DTA Data
$DD42 $F0:1D42 LCD_PIX_LO Green[2:0] Blue
$DD43 $F0:1D43 LCD_PIX_HI Red Green[5:3]
$DDA0: Wavetable Header, and SAM2695 (F256 Gen 2 only)

Main page: Use the Sam2695 Dream MIDI chip

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DDA0 $F0:1DA0 R MIDI_STATUS TX_EMPTY RX_FULL — — — — — —
$DDA1 $F0:1DA1 RW MIDI_FIFO_DATA_PORT Data
$DDA2 $F0:1DA2 MIDI_RXD_COUNT Rx FIFO Data count (12-bit)
$DDA4 $F0:1DA4 MIDI_TXD_COUNT

The SAM2695 drives the hardware MIDI jacks.

Writing to $DDA1 also gets written to the wavetable pin headers.

$DDB1: VS1053b MIDI Port (F256 Gen 2 only)

The rest of the VS1053b is up at $D700.

MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DDB1 $F0:1DB1 W Data
$DDC0: Optical Keyboard Controller (F256K2 Only)
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DDC0 $F0:1DC0 OPT_KBD_DATA FIFO queue. Each event is two 8-bit reads from here
$DDC1 $F0:1DC1 R OPT_KBD_STATUS MECH — — — — — — FIFO_EMPTY
MECH = No optical keyboard if set
$DDC2 $F0:1DC2 OPT_KB_COUNT Number of events in optical keyboard queue (12-bit)

Each event (keydown, keyup) re-sends the entire keyboard matrix in 8 events, corresponding to rows 0-7. Each row has 9 columns across its two event bytes:

Event Data
Byte 7 6 5 4 3 2 1 0
0 Row number (0-7) — — — Col8
1 Col7 Col6 Col5 Col4 Col3 Col2 Col1 Col0
$DE00: Integer Math Coprocessor
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DE00 $F0:1E00 RW MULU_A Multiplication A (Unsigned 16-bit)
$DE02 $F0:1E02 RW MULU_B Multiplication B (Unsigned 16-bit)
$DE04 $F0:1E04 RW DIVU_DEN Division Denominator (Unsigned 16-bit)
$DE06 $F0:1E06 RW DIVU_NUM Division Numerator (Unsigned 16-bit)
$DE08 $F0:1E08 RW ADD_A Addition A (Unsigned 32-bit)
$DE0C $F0:1E0C RW ADD_B Addition B (Unsigned 32-bit)
$DE10 $F0:1E10 RW MULU Multiplication A×B Result (Unsigned 32-bit)
$DE14 $F0:1E14 RW QUOU Quotient of Num/Den (Unsigned 16-bit)
$DE16 $F0:1E16 RW REMU Remainder of Num/Den (Unsigned 16-bit)
$DE18 $F0:1E18 RW ADD_R Addition A+B Result (Unsigned 32-bit)

Multiplication, division, and addition operations are completely independent of each other. Results are available immediately.

$DF00: DMA Controller
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$DF00 $F0:1F00 RW START — — — INT_EN FILL 2D ENABLE
$DF01 $F0:1F01 W Fill data byte
R BUSY — — — — — — —
$DF04 $F0:1F04 RW Source SRAM Address (24-bit)
$DF08 $F0:1F08 RW Destination SRAM Address (24-bit)
$DF0C $F0:1F0C RW Count (24-bit, not 2D mode)
RW Width (16-bit, 2D mode)
$DF0E $F0:1F0E RW Height (16-bit, 2D mode)
$DF10 $F0:1F10 RW Source stride (16-bit, 2D mode)
$DF12 $F0:1F12 RW Destination stride (16-bit, 2D mode)

DMA only runs during VBlank, and halts the CPU to take over the entire bus. This runs at 100MHz, at 8 bits (gen 1) or 16 bits (gen 2) wide.

IO Page 1

$C000: Text Mode Font Sets
MMU Flat R/W Name Description
$C000 - $C7FF $F0:2000 - $F0:27FF RW Font set 0 (256 × 8-byte chars)
$C800 - $CFFF $F0:2800 - $F0:2FFF RW Font set 1 (256 × 8-byte chars)

Characters are 8×8 pixels. Each byte is an 8-pixel row of bits, with MSB at the left. 8 rows top to bottom.

$D000: Graphics CLUTs
MMU Flat R/W Name Description
$D000 - $D3FF $F0:3000 - $F0:33FF RW Graphics CLUT 0 (256 × BGRx)
$D400 - $D7FF $F0:3400 - $F0:37FF RW Graphics CLUT 1 (256 × BGRx)
$D800 - $DBFF $F0:3800 - $F0:3BFF RW Graphics CLUT 2 (256 × BGRx)
$DC00 - $DFFF $F0:3C00 - $F0:3FFF RW Graphics CLUT 3 (256 × BGRx)

IO Page 2

$C000: Text Screen Character Matrix
MMU Flat R/W Name Description
$C000 - $DFFF $F0:4000 - $F0:5FFF RW Text screen character matrix

1 byte per character, 40 or 80 characters per row, 25|30|50|60 rows in the matrix. Each character byte refers to an entry in the currently selected font set.

80×60 characters uses 4800 ($12C0) bytes, which is only a bit more than half the 8k allocation.

Size of matrix
Rows 40 column 80 column
25 1000, $03E8 2000, $07D0
30 1200, $04B0 2400, $0960
50 2000, $07D0 4000, $0FA0
60 2400, $0960 4800, $12C0

IO Page 3

$C000: Text Screen Color Matrix
MMU Flat R/W Name 7 6 5 4 3 2 1 0
$C000 - $DFFF $F0:6000 - $F0:7FFF RW Text screen color matrix
FG color (0-15) BG color (0-15)

Exact same layout as the character matrix. One color matrix byte associates to one character matrix byte at the same offset.

Retrieved from "https://f256wiki.wildbitscomputing.com/index.php?title=IO_Pages&oldid=38500"