User contributions for WF

4 January 2026

• 21:4521:45, 4 January 2026 diff hist +281‎ m WF FPGA Ideas ‎ →‎Bitstream readers/writers Tag: Visual edit
• 20:4120:41, 4 January 2026 diff hist +714‎ m IO Pages ‎ →‎$D6A7: F256k Series LEDs Tag: Visual edit
• 20:4120:41, 4 January 2026 diff hist +2‎ WF16 Video Architecture ‎ →‎Sprites Tag: Visual edit
• 19:0719:07, 4 January 2026 diff hist +870‎ m WF16 Video Architecture ‎ →‎Tiles Tag: Visual edit
• 19:0019:00, 4 January 2026 diff hist +822‎ m WF FPGA Ideas ‎ →‎Wavetable Audio Tag: Visual edit
• 18:5618:56, 4 January 2026 diff hist +189‎ m WF16 Video Architecture ‎ →‎HDMA Tag: Visual edit
• 18:5418:54, 4 January 2026 diff hist +291‎ m WF FPGA Ideas ‎ →‎Bitstream readers/writers Tag: Visual edit

2 January 2026

• 20:3820:38, 2 January 2026 diff hist +77‎ m WF16 Video Architecture ‎No edit summary Tag: Visual edit
• 20:2420:24, 2 January 2026 diff hist +20‎ m Hardware ‎No edit summary
• 20:2320:23, 2 January 2026 diff hist 0‎ m Hardware ‎ →‎Hardware Overview and Comparison Tag: Visual edit
• 20:2220:22, 2 January 2026 diff hist −17‎ m Hardware ‎ →‎Hardware Overview and Comparison Tag: Visual edit
• 20:1820:18, 2 January 2026 diff hist 0‎ m Hardware ‎ →‎Hardware Overview and Comparison Tag: Visual edit
• 20:0620:06, 2 January 2026 diff hist +306‎ Hardware ‎ →‎Hardware Overview and Comparison: Added FPGA descriptions Tag: Visual edit

31 December 2025

• 21:4621:46, 31 December 2025 diff hist +203‎ m Foenijs ‎No edit summary Tag: Visual edit
• 21:4321:43, 31 December 2025 diff hist −24‎ m Foenijs ‎ →‎CPU Tag: Visual edit
• 21:4321:43, 31 December 2025 diff hist +1,787‎ N Foenijs ‎ Created page with "[https://white-flame.com/foenijs/ Foenijs] is a web-based emulator, whose unique purpose is ease of use in demonstrating the platform, as well as being a full-featured emulator. == Current Status == === '''CPU''' === * 65c02 and 65816 fully implemented, cycle-accurate. * Powerful debugging features (no labels yet, though). * '''Turbo mode''' still emulates the entire machine, stopping to display a frame every 100ms. <code>mandel.bas</code> turbos to 70MHz on an AMD 79..." Tag: Visual edit
• 19:4919:49, 31 December 2025 diff hist +13‎ m User:WF ‎No edit summary Tag: Visual edit

30 December 2025

• 20:3720:37, 30 December 2025 diff hist +181‎ m WF FPGA Ideas ‎ →‎Bootstrap and Machine Identity Tag: Visual edit
• 20:0420:04, 30 December 2025 diff hist +820‎ m WF FPGA Ideas ‎ →‎Wavetable Audio Tag: Visual edit
• 19:4119:41, 30 December 2025 diff hist +118‎ m WF FPGA Ideas ‎ →‎Wavetable Audio Tag: Visual edit
• 19:3319:33, 30 December 2025 diff hist +509‎ m WF FPGA Ideas ‎No edit summary Tag: Visual edit
• 18:4318:43, 30 December 2025 diff hist +123‎ m WF FPGA Ideas ‎ →‎SDCard Tag: Visual edit
• 18:4218:42, 30 December 2025 diff hist +48‎ m WF FPGA Ideas ‎No edit summary Tag: Visual edit
• 18:3618:36, 30 December 2025 diff hist +221‎ m WF FPGA Ideas ‎No edit summary Tag: Visual edit
• 17:3117:31, 30 December 2025 diff hist +99‎ m WF FPGA Ideas ‎ →‎RLE Format(s) Tag: Visual edit
• 17:2817:28, 30 December 2025 diff hist +223‎ m WF16 Video Architecture ‎ →‎HDMA Tag: Visual edit
• 17:1917:19, 30 December 2025 diff hist −93‎ m WF16 Video Architecture ‎ →‎HDMA Tag: Visual edit
• 15:2315:23, 30 December 2025 diff hist −2‎ m IO Pages ‎ →‎$C000 Gamma Lookup Tag: Visual edit
• 04:2904:29, 30 December 2025 diff hist +249‎ WF16 Video Architecture ‎ →‎HDMA Tag: Visual edit

29 December 2025

• 19:4019:40, 29 December 2025 diff hist +398‎ WF16 Video Architecture ‎ →‎Global settings Tag: Visual edit
• 19:3719:37, 29 December 2025 diff hist +290‎ WF FPGA Ideas ‎ →‎DMA/Blitter Tag: Visual edit
• 19:2519:25, 29 December 2025 diff hist +1,374‎ WF16 Video Architecture ‎ →‎Alpha Transparency Tag: Visual edit
• 04:0204:02, 29 December 2025 diff hist +285‎ FPU Accumulator ‎No edit summary Tag: Visual edit

28 December 2025

• 21:5721:57, 28 December 2025 diff hist +1‎ WF16 Video Architecture ‎ →‎Indexed Bit Depth Tag: Visual edit
• 21:5321:53, 28 December 2025 diff hist +164‎ WF16 Video Architecture ‎ →‎Alpha Transparency Tag: Visual edit
• 21:3521:35, 28 December 2025 diff hist +912‎ WF16 Video Architecture ‎ →‎Alpha Transparency Tag: Visual edit

27 December 2025

• 18:3518:35, 27 December 2025 diff hist +3,170‎ WF FPGA Ideas ‎No edit summary Tag: Visual edit

26 December 2025

• 14:4614:46, 26 December 2025 diff hist +64‎ FPU Accumulator ‎No edit summary Tag: Visual edit
• 04:5304:53, 26 December 2025 diff hist +247‎ WF FPGA Ideas ‎No edit summary Tag: Visual edit
• 04:4504:45, 26 December 2025 diff hist +114‎ WF16 Video Architecture ‎No edit summary Tag: Visual edit
• 04:3504:35, 26 December 2025 diff hist +22‎ WF16 Video Architecture ‎No edit summary Tag: Visual edit
• 04:3404:34, 26 December 2025 diff hist +98‎ WF16 Video Architecture ‎No edit summary Tag: Visual edit
• 04:2904:29, 26 December 2025 diff hist +540‎ FPU Accumulator ‎No edit summary Tag: Visual edit
• 04:1304:13, 26 December 2025 diff hist +19‎ FPU Accumulator ‎No edit summary Tag: Visual edit
• 04:1104:11, 26 December 2025 diff hist +2,646‎ N FPU Accumulator ‎ Created page with "This design for a better FPU block for 8/16 bit access, which also integrates 32-bit integer processing. While it's 32 bits, copying around 32-bit values with the CPU is mostly avoided. There are 256 32-bit registers (TBD- RAM or FPGA registers. Former allows swapping in new sets) and one 32-bit accumulator. Any of these can hold useful constants (including 0, 1, etc) for reference. It's similar to the 6502 accumulator and zeropage values. Commands are issued by writin..." Tag: Visual edit
• 03:3103:31, 26 December 2025 diff hist −9,182‎ WF FPGA Ideas ‎ Replaced content with "WF16 Video Architecture FPU Accumulator" Tags: Replaced Visual edit
• 03:3003:30, 26 December 2025 diff hist +9,181‎ N WF16 Video Architecture ‎ Created page with "== Global settings == CRT emulation, only for low resolution layers. 640x480 for 4:3 output, or 960x540 for 16:9 output, if bandwidth can run it. Non-integer pixel aspect flags, again only for low res layers. Match 320x200 and 256x200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extendin..." Tag: Visual edit
• 03:2603:26, 26 December 2025 diff hist +3,132‎ WF FPGA Ideas ‎No edit summary Tag: Visual edit

25 December 2025

• 22:1622:16, 25 December 2025 diff hist +502‎ WF FPGA Ideas ‎No edit summary Tag: Visual edit
• 21:4821:48, 25 December 2025 diff hist +5,596‎ N WF FPGA Ideas ‎ Created page with "== Global settings == CRT emulation, only for low resolution layers. 640x480 for 4:3 output, or 960x540 for 16:9 output, if bandwidth can run it. Non-integer pixel aspect flags, again only for low res layers. Match 320x200 and 256x200 non-square aspects blended on a 480p/540p base output. Keep it at 60Hz Select 50 or 60 Hz in any resolution. Ditch 70Hz, as nothing syncs to that in the PC space for compatibility. 50Hz is much lower priority, but can be done by extendin..." Tag: Visual edit